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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Maxwell who wrote (33786)7/1/1998 1:24:00 AM
From: Paul Engel  Respond to of 1571939
 
Maxwell - Re: " Some people have said that out of these 70 nstructions only 17 are new and the other 53 are just the old MMX? Is this statement true or false? "

False.

There are 70 new instructions in addition to the 57 older MMX instructions.

The KNI operate on Double Precision Floating Point data - AMD's 3DNOW is single precision.

Here's a URL (below) that may help you.

Paul

{=====================}

Programmer Says He Cracked Katmai 3-D Instructions

by Alexander Wolfe, EE Times

May 15, 1998 (01:19 P.M.)

techweb.com

Intel's closely held instruction set for its upcoming Katmai processor has been cracked, an independent software expert said Friday.

Katmai, an advanced 32-bit processor scheduled to hit the market next year, incorporates 70 new floating-point instructions that are intended to accelerate 3-D processing. Observers originally called the
code "MMX2," because it was seen as a next-generation enhancement to Intel's original 57 Pentium multimedia instruction-set extensions. However, earlier this year, Intel said the 70 instructions would be
officially named the "Katmai new instructions," or Katmai NI.

Santa Clara, Calif.-based Intel has declined to publicly release details of the instruction set. However, the semiconductor giant reportedly briefed select programmers at the Computer Game Developers
Conference earlier this month in Long Beach, Calif.

Now, the software expert, Clive Turvey, has posted a list of Katmai NI instructions and opcodes. Turvey said he uncovered the instructions by examining an application program Intel publicly posted at an online
site.

The instructions include a rich complement of add, prefetch, and move operations, among others.

In addition, Turvey said he believes Katmai includes a set of registers, XMM0 through XMM7. "I believe [these] will be a set of floating-point MMX registers separate and distinct from the integer registers MM0 thru 7," Turvey said. "Given the size of the context space conveniently provided by the FXsave/FXrstor instructions, this would allow each register to be 40 bytes in size."

Turvey added that the application he examined included a lot of references to two items, SS and PS. "I'm not sure if this means single/double precision or primary/secondary registers," he said. "In any case, Intel's floating-point units typically deal with 80-bit floating-point values. Given eight registers, you could easily
represent two 4-by-4 matrices."

Copyright 1998, CMP Media Inc.