Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : CYRIX / NSM -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (27966)	7/6/1998 8:50:00 PM
From: AB	Read Replies (2) \| Respond to of 33344

Here's a rather sobering opinion re x86 CPU prices from LB: MUCH LOWER PROCESSOR PRICE ESTIMATES APPEAR IN THE TRADE PRESS. Because INTC releases upcoming price cuts to customers (under nondisclosure) months in advance, the trade press has done a reasonable job of ferreting out changes. Consequently, we are disturbed to note that PC Week's 6/22 issue shows much steeper price cuts during the next few months than previously anticipated: The Pentium-II/400, now at $722, is estimated to be at $375 in October (old est.: $530), and the Pentium-II/350, now at $519, is estimated to be at $210 in October (old est.: $316). So what's the better play, short INTC or buy NSM? Also infoworld.com Anthony

To: Scumbria who wrote (27966)	7/7/1998 7:51:00 AM
From: Ritz	Read Replies (1) \| Respond to of 33344

Scumbria: Re: "but there is nothing inherent about the x86 architecture which requires lower clock speed [than the Alpha chip]. For example, PII runs at a higher clock speed than Power PC, Sparc or Mips." I disagree. Alpha's clock speed advantage comes from its simpler pipelines, which allow shorter speed paths and thus shorten latencies. Although design choices play a part in this (no out-of-order execution for Alpha, for example), it is primarily enabled by Alpha's stripped to the limit instruction set, which is not only far smaller than X86's, but far smaller (and simpler) than the other RISC instruction sets as well. -Ritz