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To: kash johal who wrote (28001)7/7/1998 8:14:00 PM
From: Scumbria  Read Replies (1) | Respond to of 33344
 
You unfortunately hit several limits: A) Die size becomes excessive and yields drop off exponentially and costs increase accordingly.

Kash,

This point is true, but is mitigated by a number of other circumstances.

1.) Smaller feature sizes of modern processes allow for many more transistors on a die.

2.) It is widely recognized that the excessive instruction level parallelism of processors like K6 and PII is unnecessary. MII has only two execute pipes, but runs considerably faster at the same clock speed than PII or K6. AMD and Intel could reduce architectural complexity (and free up some die area) with very little loss of architectural performance.

Scumbria



To: kash johal who wrote (28001)7/8/1998 7:41:00 AM
From: Ritz  Respond to of 33344
 
Kash:

Hmm....thinking about it a bit and Scumbria does have a point. Design certainly does play a role and Yousef's focus on clock speeds is too simplistic. How about:

(Chip performance/voltage) * (yield/die size) = Process performance

-Ritz


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