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To: wmf who wrote (9118)	7/8/1998 9:31:00 PM
From: Scumbria	Respond to of 11555

For the integrated chip you might actually end up with a more expensive package because you exchange one big package with tight processor specs against a small package with tight specs and another small package with loose specs. Package cost is based mostly on pin count. I don't know what National has planned, but it is not hard to imagine a PCOAC in a very small pin count package, and thus low cost. If all the functionality of the computer is contained within the die, why do you need a lot of pins? Scumbria

To: wmf who wrote (9118)	7/9/1998 6:10:00 PM
From: Rob S.	Respond to of 11555

The package I/O interconnects may be reduced in the integrated SOC and some reduction in board space, etc. may lower cost a bit. The testing of SOCs is a big issue. As these parts get more complex the verification and testing becomes more difficult. I don't know if it is a direct geometric progression but it is more than a simple multiplier increase. I think the marketing aspects of the move are as or more important determinants than the technical aspects. The Sony Playstation uses one of the first true SOCs. That is an application on which the manufacturer controlled all aspects of software and hardware. It also is "special purpose" in that it's not an open architecture on which you are running evolving software or interfacing other people's hardware. The PC is no such animal - if anything is plagued by it's lax and tumultuous openess. An SOC makes great sense where the bounds of it's performance requirements can be controlled long enough to return the large initial investment. Take putting the graphics processor on the SOC with the uP and logic fucntions. The graphics companies have been increasing performance and features by degrees of magnitude with new generations coming out within several months of each other. The chips have grown so complex that they are beginning to rival uPs in number of circuits. And they are trending along on their own SOC type path with the inclusion of graphics memory and enhanced I/O functionality. So where do you cast the concrete to include the graphics engine in the uP SOC? Not that simple of a call - miss the performance curve and you divorce yourself from a significant segment of the market.