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To: Jeff Fox who wrote (59734)	7/11/1998 2:55:00 PM
From: Jim McMannis	Read Replies (3) \| Respond to of 186894

Jeff, RE:"Line yields - This is perhaps an industry "dirty little secret", but all fabs do not count zero yield wafers in thier normal yield numbers. Wafers "zero" with breakage and gross misprocessing. Instead there is a separate statistic called line yield - the ratio of wafers with some yield to total wafers processed. Intel has very high line yields. For AMD who knows; they could be reporting "excellent yields" while throwing away up to half the wafers under the unreported line yield category." Thanks, I didn't know that. My edcuation here about chip making hasn't been an easy one because of the blatant hatred of AMD, Intel, NSM etc. getting in the way of sensible posts like yours. I've archived your post with the others that actually gave an unbiased opinion. As far as the throw away wafers, I'm going to check into that. Thanks, Jim

To: Jeff Fox who wrote (59734)	7/11/1998 3:40:00 PM
From: Elmer	Read Replies (1) \| Respond to of 186894

Jeff, my I add one more thing you and Paul left out? Burnin. A poorly controlled fab process may require a number of hours of burnin at high cost to meet quality requirements. A clean process may require no burnin at all, or only limited or sample burnin. As for test, a well controlled process may not require testing at both temperature extremes. A process running across several sigma could require double the test socketings and double the cost. Once again these and all the examples you and Paul provided, shows how only looking at die size is a poor estimate of product cost. EP