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Technology Stocks : Cymer (CYMI) -- Ignore unavailable to you. Want to Upgrade?

To: DTselentis who wrote (18463)	7/15/1998 12:28:00 AM
From: BillyG	Respond to of 25960

Toshiba combines DUV and e-beam.......... eet.com Toshiba describes breakthrough in processor lithography By Anthony Cataldo TOKYO - Engineers from Toshiba Corp. say they have cleared two hurdles in the fabrication of future microprocessors by finding ways to improve production throughput and to enhance the precision of circuits with gate lengths of 0.15 micron or less. Toshiba's method, which combines deep-ultraviolet optical technology and electron-beam lithography in a single manufacturing process flow, has been broached by several research groups over the past four years. These researchers say that "mixing and matching" deep-ultraviolet technology with the superior resolution of e-beam equipment is the best way to build devices that offer pattern resolutions as low as 100 nm, but which can be manufactured at a faster rate using today's optical steppers. Toshiba will present its findings this week at the Microprocesses and Nanotechnology Conference in Kyoungju, South Korea. Toshiba's method is similar to other proposals in many respects. After the wafer is coated with resist, those mask patterns that are less than 150 nm long are handled first, using e-beam lithography equipment. Any patterns with resolutions above 150 nm are treated in the next step, using deep-UV steppers. (Toshiba used its own EX-8D EB writer, a Nikon Scanning KrF deep-UV stepper and a negative-tone resist that works with both e-beam and deep-UV). But the approach differs from others in two key ways, according to Toshiba. First, to increase production speed, the company used a biased deep-UV exposure tool that takes over part of the e-beam resist dosages, thus reducing the exposure time needed for the e-beam by 30 percent, the company said. And wafer throughput is seven wafers per hour - almost three times faster than using electron beam only, according to Toshiba. The company also claims it has found a way to improve the alignment accuracy of circuit patterns created by both electron-beam and deep-UV. Normally, the overlay error - which measures misalignment between circuit patterns - is an 80 nm for patterns created by both lithography technologies, and "80 nanometers is not good enough," said Shunko Magoshi, a processs-technology research specialist at Toshiba's Microelectronics Engineering Laboratory (Yokohama, Japan). "This could affect device performance." To get around the problem, Toshiba turned to Nikon's scanning deep-UV stepper, with better overlay characteristics, and developed algorithms to under-size and oversize the patterns. The result is an overlay accuracy of 50 nm, according to Toshiba. Magoshi said that the technology will be used for Toshiba RISC processors sometime after 2000 but that it won't be applicable to future DRAM devices, which will rely more on sophisticated capacitor structures. "This technology can be used for any type of logic device. The MPU requires smaller gate lengths than ASICs," he said.

To: DTselentis who wrote (18463)	7/15/1998 1:36:00 AM
From: Elroy Jetson	Read Replies (3) \| Respond to of 25960

The last 10% of the Intel Conference Call Q & A is VERY informative. intel.broadcast.com Intel will produce 0.18 scale chips mid-year 1999 to avoid a need for 300 mm wafers at that time to maintain economies. This 0.18 mm equipment must be purchased by the end of this year. It's my understanding that it takes at least 6 months for the Cymer lasers to be built into finished stepper products. I think I recall Cymer books sales when its shipped to the stepper maker. If this is all true, the Cymer lasers destined for Intel steppers had to be booked as sales prior to June 1998. .... Comments ???