News ! Teradyne shows Test System
Thursday July 16, 7:00 am Eastern Time
Company Press Release
SOURCE: Teradyne, Inc.
Teradyne Shows New Test System for High-Bandwidth RAMs; ARIES Tests SLDRAMs at SEMICON West
SAN JOSE, Calif., July 16 /PRNewswire/ -- Teradyne (NYSE: TER - news) is demonstrating its advanced technology for testing high-bandwidth RAMs at SEMICON West here this
week. The ARIES RAM test platform tests up to 16 devices in parallel at an I/O bandwidth of 1.6 Gbytes/second, providing the lowest cost to test for the newest-generation devices
such as Direct Rambus(TM) DRAMs, SLDRAMs, and fast SSRAMs. Teradyne's demonstration of SLDRAM test shows how the system's logic vector memory and algorithmic memory
pattern generator work together to test the device's array and interface at the SLDRAM's full I/O bandwidth of 800 Mbytes/sec.
Multiple customers have installed ARIES test systems since its introduction last December; said Glenn Farris, ARIES Product Manager; they are using the system to test the
new-generation high-speed devices in engineering and production. Teradyne has been chosen by Rambus as a technology partner, and by the SLDRAM consortium as its reference
standard test system.
The High-Bandwidth Test Requirement
Direct Rambus-and SLDRAM-generation technology has changed the memory test requirement, Farris said, because it combines a high bandwidth logic interface bus with a
high-density DRAM. While low-speed test of the DRAM array is still appropriate for finding some fault types, it does not provide all the necessary fault coverage, even when combined
with a separate high-speed logic test of the device's interface. ''When high-bandwidth RAMs are used in computers and advanced communications devices, a memory cell that fails at
the new higher operating speeds can result in a spreadsheet error or a corrupt database,'' he said. ''Customers can't tolerate that.''
The solution is to test the performance of the whole memory in a single pass, at its full operating speed, including the array, the interface, and the complex interactions between them,
Farris said. ''Without that kind of comprehensive testing, you're susceptible to gaps in fault coverage. Problems like bank interactions and noise sensitivities may not be found if the
interactions between the array and the interface are not tested. Full functional algorithmic testing at speed enables the memory supplier to guarantee the total performance of
high-bandwidth memories for computer and advanced communications applications. ARIES' unique contribution is that it provides the full functionality to test the high-performance
memory behind the interface, and find all the faults in the whole device.''
This shift in test requirements is similar to one that occurred 10 years ago with the introduction of mixed-signal devices, Farris noted. In the mid-1980's, devices with mixed analog and
digital functionality were tested in two passes, first on an analog tester and then on a digital tester. As the complexity and performance of the devices increased, a new mixed-signal test
platform emerged to test the device as a whole. ''Today, single pass testing of mixed analog and digital devices is the method of choice to maximize fault coverage and minimize testing
cost,'' Farris said. ''The same transformation will soon occur in memory manufacturing, as high-performance semiconductors with mixed logic and memory reach high volume.''
Lowest Cost to Test
Although test performance requirements have increased dramatically, memory production economics cannot change, Farris said. Manufacturers require the lowest cost per bit in order
to win in the competitive memory marketplace. ARIES enables memory manufacturers to achieve the lowest cost to test in several ways:
Low Production Test Costs. By providing a test solution that includes single-pass high-speed testing, with the highest parallelism and throughput, ARIES enables
manufacturers to realize the lowest possible cost to test. ARIES tests up to 16 devices in parallel at an I/O bandwidth of 1.6 Gbit/second; its Pin Slice(TM) architecture delivers
fast DC testing and lowest test-time overhead.
Fast Ramp-up to Volume Production. ARIES' production-proven software, full integration of handling equipment, and compatibility among test systems across the production
floor speeds a manufacturer's ramp-up to volume production.
Shortest time to Maximum Yield. ARIES provides algorithmic testing at speed, a powerful suite of silicon debug tools, and the RA/Plus(TM) redundancy analyzer, which finds
every repairable die, to deliver the highest possible yields in the shortest time. ARIES' 1 Gbit Catch RAM and Data Searcher compression hardware provide fast fail capture for
redundancy repair analysis, silicon debug, and yield improvement engineering. Because ARIES' debug and characterization tools are fully integrated with its parallel operating
software, memory manufacturers can perform fast data capture and analysis in parallel, reducing the time required to achieve maximum yields.
ARIES Leverages Proven Technology
The ARIES platform leverages technology proven in Teradyne's J973 and Marlin logic and memory test systems, which have been selected by the world's leading semiconductor
producers, Farris said. ARIES' comprehensive memory test capability is based on Teradyne's 35+ years as a memory test leader; it includes at-speed algorithmic pattern generation,
redundancy analysis, and parallel bit mapping. ARIES-platform systems also include the full logic test capability of the J973 VLSI Test System, whose innovative Pattern Integrator(TM)
architecture was designed to provide seamless testing of devices combining complex logic and memory cells, with a pattern depth of up to 16M vectors for at-speed testing with no dead
cycles. The system's advanced pin electronics includes low-jitter high-speed clocks and high-speed drivers for edge placement repeatability of +/-50 ps. In addition, ARIES'
direct-connect test head design and fly-by handler contactor technology deliver high-speed test signals for at-speed performance testing.
Rambus Technology Partner
In September of last year, Rambus, Inc. announced that Teradyne was selected as a test technology partner for the Direct Rambus device. Several ARIES features have been designed in
collaboration with Rambus to focus on the testing needs of high-speed DRAMs, Farris said. ''Rambus values the partnership we have with Teradyne to develop test solutions for the
Direct RDRAM,'' said Allen Roberts, vice president and general manager of Rambus Inc [Nasdaq:RMBS - news].'s Memory Technology Division. ''Because Teradyne is a leading
supplier of high-volume production memory test systems, its development of Direct RDRAM test solutions ensures that the test infrastructure is in place to rapidly bring our high-
bandwidth interface technology to volume.''
SLDRAM Reference Standard Test System
Farris said that ARIES has also been chosen by the SLDRAM consortium as its reference standard test system. ''Teradyne's ARIES provides the leading-edge test capability our
members need to deliver the best memory performance at the lowest possible cost,'' said Farhad Tabrizi, President of SLDRAM Inc. ''With ARIES test programs and interfaces in place,
memory manufacturers can evaluate and debug silicon quickly and move into volume production.'' In April, he said, Micron Technology, Inc. announced shipment of the first 64M
SLDRAM samples to major computer OEMs and SLDRAM supporters for engineering evaluation. ''SLDRAM is real,'' Tabrizi said. ''ARIES will help our members deliver their products
to a marketplace hungry for our kind of performance and price.''
Pricing of ARIES Platform systems starts at approximately $1.3 million. System shipments are approximately 18 weeks ARO.
Teradyne is a leading manufacturer of automated test equipment and connection systems for the electronics and telecommunications industries. The Memory Test Division is
co-located in Agoura Hills and San Jose, California. Teradyne sales in 1997 were approximately $1.3 billion. Teradyne's Internet address is www.teradyne.com.
SOURCE: Teradyne, Inc.
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