To: Gary Ng who wrote (61079 ) 7/24/1998 12:56:00 AM From: Paul Engel Respond to of 186894
Gary & Intel Investors - Yet another Story on Intel, Copper & 0.18 micron process and products. Hear it is. Paul {============================}techweb.com Intel Plots A Safer Course Than Rivals (07/23/98; 7:49 p.m. ET) By Andy Patrizio, TechWeb While its competitors pursue huge leaps in technology and performance, Intel is taking a more deliberate and steady approach, broadening all three lines of its P6 family and bringing new technologies into the central processing unit (CPU) mix. The company obviously isn't scared of Advanced Micro Devices, which announced an agreement to license the new copper technology from Motorola and expects to have 1-gigahertz K7 chips on the market by 2000, or Compaq's Alpha chip, which could hit 1 GHz by next year, according to Alpha Processors, a Samsung subsidiary that sells Alpha-based hardware. Intel (company profile) is also going slow on the new copper technology from Motorola, and doesn't plan to use it until it moves to the 0.13 micron die size in 2001, which will be in the Merced era. "Are we worried? No," said Christine Chartier-Morris, an Intel spokeswoman. "From an Intel perspective, we are very confident in what our road map is and the needs of our customers." That road map includes getting all of its manufacturing facilities converted to the 0.25 micron die by the end of this quarter, and into 0.18 micron by next year. The first 0.18 micron chips will be Cascades and Coppermine, which are part of the Xeon and Pentium II families, respectively. Coppermine is set for both desktop PCs and mobile computers, while Cascades will go in workstations and servers. Cascades and Coppermine will be the second generation of chips with the Katmai instruction set. Katmai is due in the first half of 1999, while Cascades and Coppermine come in the second half. Intel won't disclose the speeds of Cascades and Coppermine, but they will be faster than the 500 MHz promised for Katmai and Tanner, a Xeon chip due in the first half of 1999, Chartier-Morris said. On the low end of the P6 line is Celeron, which is getting a boost in speed as well. In this quarter Intel will ship the Mendocino family, which comes with 128K of L2 cache, an external cache that stores the CPU's most recently executed instructions, boosting performance by as much as 20 percent. The first generation of Celerons, which went from 233 MHz to 300 MHz, lacked an L2 cache. The new Celerons will come in 300-MHz and 333-MHz configurations by the end of this quarter, with a 366-MHz chip due in the first half of 1999. Intel is also moving into the graphics market on the high and low ends. On the low-end, the company is planning to integrate the i740 3-D chip into the Whitney chip set that will be used by the Mendocino chips. On the higher end of the scale, the company bought an 8 percent stake in graphics developer Evans & Sutherland Computer earlier this week. Intel can afford to go slow, said one analyst, because it covers so much territory and is in a leadership position. "If you're not the leader, you've got to do something to get people's attention and do something to get people to buy from you and not [from] the safe choice," said Nathan Brookwood, senior analyst for microprocessors at Dataquest in San Jose, Calif. Brookwood said Intel made a very clever move stratifying its lines. "Xeon won't show up in CompUSA, and Celeron isn't likely to show up in corporate America," he said. Before, when the plan was to sell the fastest chip for the most money, and over time it would fall in price as faster chips replaced it, there was nothing to stop server vendors from buying a cheaper chip for its servers. "By putting up these little firewalls, now they have a barrier where the people who need to build servers have to buy a more expensive chip," said Brookwood. Intel also said it was planning price reductions for next week, but wouldn't say which lines are being cut.