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Technology Stocks : LAST MILE TECHNOLOGIES - Let's Discuss Them Here -- Ignore unavailable to you. Want to Upgrade?

To: MikeM54321 who wrote (1700)	7/27/1998 8:03:00 PM
From: DenverTechie	Read Replies (1) \| Respond to of 12823

Mike - this is a confusing area of technology and I may not be the best person to answer this question. To fully understand what is being said, an in depth knowledge of SONET and its framing structure are necessary. I think I may be a little behind on this, because the last time I checked, the only framing formats that were supported directly by SONET were the OC (optical carriers) family like OC-3, OC-48, etc. and ATM. Even regular asynchronous formats like DS-1 and DS-3 had to converted by multiplexers into OC format before being framed into SONET. Unless there is a new supported IP protocol over SONET which this Gilder chap seems to be implying. Then it would be okay. But his statement of "physical layer infrastructure becoming more abundant" is gobbeldygook nonsense since the same supported framing formats, but just more SONET out there, makes no difference. Its the part about being more capable that I am not sure of. As far as the percentages of network topologies planned, I can show you 8 different studies that say 8 different breakdowns of this, depending on the type of network (enterprise, private, backbone, general public, etc.) to support any position I'm trying to advance. As you say, there are large amounts of ATM being bought at all levels (for good reason), so I'm not sure where he gets these figures from. Sorry I couldn't be of more help on this one, but sometimes I have to know what I don't know and not claim to know it.

To: MikeM54321 who wrote (1700)	7/28/1998 9:33:00 AM
From: Frank A. Coluccio	Read Replies (2) \| Respond to of 12823

Mike, All, What do you think about the direction this firm (TranSwitch) is taking in this release? I could almost _hear_ the indigestion that this one is causing in some circles. Preserve the visibility of the 64 kbps DS0? <grin> Regards, Frank C. ================= Returning to its Sonet roots, TranSwitch updates devices July 28, 1998 ELECTRONIC ENGINEERING TIMES via NewsEdge Corporation : Shelton, Conn. - TranSwitch Corp., the telecom IC company that was weaned on Sonet before expanding into asynchronous transfer mode (ATM), is returning to a new generation of Sonet multiplexers and cross-connects with a revised vision of the architectures required. As Sonet picks up steam as an Internet access technology, TranSwitch is keeping a strong hand in framer devices for pleisochronous digital hierarchy (PDH) services, while assuming that PDH networks must coexist with SDH/Sonet broadband systems. After releasing a quartet of WAN products in June, including an advanced mapper and multiple-service framers, TranSwitch's next step is to roll out a 3.3-V overhead termination device called PHAST-1 this week. It will be followed by a dedicated HDLC controller in the autumn. For TranSwitch, functions like overhead termination and HDLC-based serial control are moving to the forefront. So are embedded RISC cores and increasing overall integration of digital devices, in an effort to combine elements of overhead processing, service mapping and Sonet payload envelope processing. Last summer, TranSwitch brought in Deepak Rana, an executive with experience at Bell Labs and IBM, as Sonet/ SDH product marketing manager, to reformulate its silicon strategy for high-layer processing in next-generation Sonet designs. While physical-layer specialists may concentrate on very high-speed backbones, Rana said it was equally important for the digital logic devices used in Sonet transmission systems to preserve the visibility of DS-0 (64-kbit/second) data streams. On the surface, a design strategy that de-emphasizes simple single-channel framers may seem incongruous, given the fact that TranSwitch included three new framers among the four Sonet products introduced at the June Supercomm show. But Rana pointed out that advanced framer architectures support new types of feature sets, tailored for byte-synchronous and asynchronous services. The DS1MX7 seven-channel mapper was a critical chip for bringing together PDH and SDH worlds, Rana said. When used in a Sonet terminal multiplexer, it can link to a line-interface unit in a byte-synchronous mode using quad T1 framers, or directly in asynch mode. It can also connect to multiple DS-0 64-kbit services in a byte-synch mode-all within one system from a common mapping device. But TranSwitch is finding a secondary use for the DS1MX7 as a byte-synch frame-relay Internet access system for customer premises use. Here, the mapper links directly to the PHAST-1 chip that will be introduced this week for add-drop termination, and to a multichannel HDLC device for direct connections to local buses. The PHAST-1 is an example of the need for lower power dissipation and greater feature sets even at the lower Sonet speeds, such as STS-1 (51 Mbits/s). The device is intended to simultaneously provide section, line and path termination, along with alarm detection and generation. An on-chip RAM stores overhead bytes. The move to multiple-channel HDLC will be a new one for TranSwitch. Rana said the company is not ready to provide full details on the device yet, except to say that it will make use of programmable RISC cores. TranSwitch has experience in its own microprogrammed engine through the SARA and SARA Lite, used for ATM segmentation and reassembly. The HDLC processor, however, will be based on a standard MIPS instruction set. No surprises The beauty of the mix-and-match approach across PDH and SDH worlds, Rana said, is that TranSwitch does not have to be caught by surprise as systems emerge that combine processing layers, such as packet over Sonet or ATM cells over optical WDM (wavelength-division multiplexing) layers. As Sonet moves into the Internet service-provider market, Rana said, "it's a misnomer to call it a transmission system any more. It's an Internet access system." The only thing that is off the table in current planning, Rana said, is to divorce design concepts from silicon by moving to an intellectual-property approach of the sort adopted by newcomers like Cimaron Communications Inc. (Andover, Mass.). "People always ask us to provide them with soft macros, and in almost all circumstances we say no," Rana said. "No matter how I look at the market dynamics, providing an intellectual-property core for higher-layer Sonet functions makes zero sense." Copyright - 1998 CMP Media Inc. <<ELECTRONIC ENGINEERING TIMES -- 07-27-98, p. PG22>> [Copyright 1998, CMP Publications]