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Technology Stocks : CYRIX / NSM -- Ignore unavailable to you. Want to Upgrade?

To: Steve Porter who wrote (28568)	7/28/1998 8:10:00 PM
From: Joe NYC	Read Replies (2) \| Respond to of 33344

From Pricewatch: pricewatch.com They added new processors, including K6-2 333 amd MII-333. 2 vendors have expected arrival date for K6-2 333: 204.57.71.4@ctd+3+AND+@contents+AMD+AND+@contents+K6+AND+@contents+2+AND+@contents+333+AND+@contents+3DNOW&catd=3&cn=CPU&cr=CPU+AMD+K6-2+333+3DNow&n=47&CiCodePage=Windows-1252&a=0 Nobody even has any idea when to expect M-II 333: 204.57.71.4@ctd+3+AND+@contents+CYRIX+AND+@contents+MII+AND+@contents+333&catd=3&cn=CPU&cr=CPU+Cyrix+MII-333&n=45&CiCodePage=Windows-1252&a=0 Just FYI, P-II 450 is available: 204.57.71.4@ctd+3+AND+@contents+PENTIUM+AND+@contents+II+AND+@contents+450*&catd=3&cn=CPU&cr=CPU+Pentium+II+450&n=28&CiCodePage=Windows-1252&a=0 Joe

To: Steve Porter who wrote (28568)	7/28/1998 8:24:00 PM
From: Scumbria	Respond to of 33344

What is wrong with the following scenario happening: Add a "pre-decode" unit which peeks into the instructions and scans for those which will need data not in the cache and go and get it. Steve, x86 processors generally have a pipeline similar to the one described here: prefetch\|decode\|address calc\|address translate/cache lookup\|execute\|complete The address calculation generally depends on the results from previous instructions(i.e. experiences hazards.) The address calculation unit is large and draws a lot of power. Attempting to duplicate this hardware could be very costly. Speculative address translation and cache lookup would cause contention and hazards with the tlb/cache. Adding additional read ports to the tlb/cache would be totally out of the question because of complexity and impact on clock speed. There are other issues associated with bus/memory contention which would also make you want to avoid a hardware based speculative cache fill. It is likely that such a scheme would actually reduce overall system performance. The most valuable architecture lesson from the 90's was that complicated speculative superscalar CPU's were a mistake. The best processors are simple ones which run at high clock rates, and have large low-latency memories onboard the CPU. Scumbria