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To: Steve Porter who wrote (28578)	7/29/1998 1:21:00 AM
From: Scumbria	Respond to of 33344

Let's say a CPU currently has: ADD EAX, EBX in the memory calc/decode stage. Well since those are both registers, the memory unit isn't in use. When not snoop into the instruction stream an instruction or two and get what it will need? Doing that will give you a couple of clocks head start at the VERY least. Steve, There are situations where address calculation can be bypassed and save a few clocks. The problem is that most x86 instructions access at least one memory location, making the case you described the exception rather than the rule. On the other hand, RISC processors do not stall the execution of load/store instructions if the previous instruction is a register-register operation. Scumbria