SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : CYRIX / NSM -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (28583)7/29/1998 11:13:00 AM
From: Nemo  Read Replies (2) | Respond to of 33344
 
Scumbria:

I noticed that sandpile.org does not list any bugs for Cyrix processors. Does this mean that the M1 and M2 are bug free or just not documented? Also, do any of the Cyrix processors have a RISC core?

Thank you.

Nemo



To: Scumbria who wrote (28583)7/29/1998 12:33:00 PM
From: Paul Engel  Read Replies (1) | Respond to of 33344
 
Scumbria - Re: "The 8086 used a sixteen bit offset from the segment register to generate the address."

Fine - what does this have to do with the fact that the 8086 CAN PRE-FETCH instructions?

Nice try at changing the subject.

Re: "The processor was serialized and had no hazards. "

What in the world are you talking about?

No hazards, huh? Were those 16 bit hazards, 32 bit hazards or sand traps?

Paul


HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2026 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News