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To: Clarksterh who wrote (2627)	7/31/1998 8:40:00 PM
From: Kirk ©	Respond to of 3696

PS What layers is it that typically use the largest dimensions? I assume interconnects, but what else? For the analog designs I've done, this layer is power/Ground/shield where the layer is mostly metal with seperations only to make the large power and ground lines and the whole thing is used for shielding ( dual purpose). regards Kirk

To: Clarksterh who wrote (2627)	7/31/1998 8:55:00 PM
From: Katherine Derbyshire	Respond to of 3696

Actually, the very top layers might be at 0.5u (or at least 0.35u, which is about the end for i-line litho) when the critical layers are at 0.08. There's a trend toward what's called hierarchical wiring, which means making the top (power) interconnect layers proportionally larger. It's attractive because the resistance of a line goes up as the line gets smaller. Hierarchical wiring could help power dissipation in some of these ultra-small geometries. Yes, the multiplier effect you mentioned will eventually happened. SVG sees non-critical DUV as a big potential market share boost for them: news.semiconductoronline.com >>PS What layers is it that typically use the largest dimensions? I assume interconnects, but what else? << The very topmost layer, where the bond pads are, is typically the largest, and things get smaller as you go down. It's a little misleading to talk about interconnects having the largest dimensions though, since interconnects account for something like 70% of the process steps, ranging from very small to very large. A microprocessor is likely to have 5-6 metal layers these days. (A number of companies, notably ICE (http://www.ice-corp.com), have posters showing a cross-section through a chip. Worth trying to track down, since actually seeing it helps put all this stuff in perspective.) Katherine

To: Clarksterh who wrote (2627)	8/1/1998 11:04:00 AM
From: Andrew Vance	Read Replies (2) \| Respond to of 3696

The last dielectric layer of the process where the metal pads are exposed for wiring bonding from the package cavity to the IC itself (called PAD layer) will always be a non critical level. PAD pitch and wire sweep along with precision of the available wire bonders makes it almost impossible to have these PADs at sub micron dimensions. You have also read above the polyimde layer for protection that, for now, is a separate overcoat layer to pad level. UTEK actually has a process that can combine both of these process levels which has not been fully implemented by the industry. Much of the issue has to do with the acceptance of the polyimide chemistry (solvent based) within the industry and a little has to do with the mix/match strategy not being accepted by many companies. This may change down the road as companies need to become more cost effective to compete. The third and fourth layers would be the metallization pads themselves and the via interconnect level just below this metal pad level that provides the pathway to the underlying levels of metal. As devices become more complex, we have moed away from 1-2 levels of metal to 4-6 levels of metal. A majority of these metal-via interconnect levels should stay above the 0.50u critical dimension. There is apparently a finite dimensional opening that a via must be relative to the thickness of the dielectric itself to allow a proper slope to the via opening thereby allowing proper deposition of the metallization into that via. Even with the incorporation of CMP (chemical mechanical polishing) there will still be a ratio of thickness of dielectric to thickness of underlying metal and the interconnect dielectric thickness to via opening ratio an issue requiring these openings to be of a non critical nature. (relative to the smallest feature sizes of the device itself). A number of the ion implant levels have typically been non critical levels since they are usually defining very large areas or pockets of ion densities for electrical characteristics. Typically there are more than 4 implant levels. So worst case scenario would be, as you suggested, that 33%-40% of all process layers might always remain as non critical levels. Finally, not being an Electrical Engineer or Physicist, as we get to 0.08u and below, we are approaching the molecular levels of many things. You may have heard of NanoFabrication being bantered about. Not being an expert, I am sure you reach a point where the dimension of an electron and the electromagnetic fields surrounding these electrons come into play and define certain critical dimensions, thicknesses of layers, and minimum isolation between levels of metal. In this last statement, think of multilevel highways and the over/under passes. You run into major barriers as you add more levels tot he highway and you are restricted to a certain finite height of each level before cars are unable to pass through each level. Enough weird science for a Saturday Morning. Enjoy the rest of your weekend. Andrew