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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Adrian Wu who wrote (35485)	8/4/1998 11:59:00 AM
From: Elmer	Read Replies (1) \| Respond to of 1574109

Re: "Why did Intel not include the option of a MB L2 for the 440EX chipset which was designed for the cacheless Celeron? The reason is because the P6 bus protocol was designed to have a separate bus for the L2 cache ("backside bus"), and not designed to accommodate an L2 on the frontside bus. Otherwise, it would make perfect sense for Intel to design the 440EX with an L2 cache option to improve the dismal performance of the Celeron." Again Adrian, what reason do you have to believe the bus protocol prevents L2 on the motherboard? That was your statement. The 440EX chipset appears to be a dumbed down 440LX. A redesign with added L2 controller would have required significant design resources. Perhaps Intel is doing the same thing with their chipsets that they are doing with their CPUs. One die may lead to several products. In any case, I can see nothing about the bus protocol that prevents MB cache, be it L2 or L3. EP