SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?


To: Gordon Hodgson who wrote (61962)8/6/1998 7:48:00 PM
From: Bill Jackson  Respond to of 186894
 
Gordon, As they say win some lose some. If you look at all sources of capacitance there will be some due to adjacent tracks and some due to the substrate and there will doubtless be some from other places.
Doubtless the techies can say more with greater precision than I can.
If the lions share is from the substrate then the speed increase will be more. If from co-channel capacitance then the substrate reduction will be less. One hopes they select conductive paths to minimize the adjacent conductor capacitance. Going to copper will allow for smaller lines and thus they can be a bit further apart and have the same resistance but lower capacitance to substrate and to each other. If they are kept the same size as before they will have lower resistance and run faster. Capacitance will be the same since dimensions are the same.
So it all depends on what aspects give the greatest capacitance?
It looks like a game of incremental gains, add 3% here and 2% there andkeep tweaking.

As I suspected though, Intel sleeps not at the switch and if and when the SOI tech has davanced to the point of significance they will be there. I suspect they have assorted projects covering all these aspects ubder way as we speak, they can afford it.

Bill

Bill