SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?


To: Paul Engel who wrote (62515)8/15/1998 1:11:00 AM
From: Elmer  Read Replies (1) | Respond to of 186894
 
Re: "One possible explanation is that in a 4-way system there is twice the heat being dissipated as in a 2 way system - 4 CPUs vs 2. Also, the 450NX chip set - does it have more than one chip? I know the 440BX has only one chip in the northbridge."

The 450NX is 4 or 5 chips, I think. And yes, this all seems to get down to air flow/heat sinks etc. DEC solved a much worse problem.

EP



To: Paul Engel who wrote (62515)8/15/1998 4:47:00 PM
From: Tony Viola  Read Replies (2) | Respond to of 186894
 
Paul, Re: "If the system designs do not provide enough heat removal, the junction temperature
of the CPU chip may exceed safe operating limits (usually around 125 to 150 C at
the CPU silicon surface - not the case temperature)."

Do you happen to know how (hopefully somehow) Intel does prediction of temperature rise in chips, modules and systems? There are simulation tools, such as finite element analysis, that will accept 3D packaging dimensions, power dissipation of all components in the package, cooling air velocity and volume, and other pertinent inputs, and predict temperatures anywhere in the package. Intel, through its long string of microprocessor, chipset, mobo and server node designs, certainly has all the experience to be able to come up with all the parametric data to plug into any simulation system. Just wondering (hope they aren't skipping an important step in the overall chip to system development process).

Tony