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To: Paul Engel who wrote (62522)8/15/1998 9:08:00 AM
From: rudedog  Read Replies (1) | Respond to of 186894
 
Paul -
Bert evidently doesn't know much about large system architecture either. Let's look at one facet of his argument.

He says 'can ultra-high bandwidth make up for poor latency?' - his answer, no. He makes the argument that RAMBUS delivers data faster than the CPQ can use it, but with greater latency than SDRAM.

I will ignore for the moment that systems of architectural interest at the moment have more than one processor. Is this clown seriously proposing that 8 processors can't eat data faster than they can get it? Does he have no understanding of cache hierarchy? But I digress...

Next generation systems will be focused on increasingly high bandwidth clustering and storage I/O. A redundant clustering interface can use 400 MB/sec per channel (800 MB/sec total) bandwidth, but latency of 500 uSec is fine. These are not UMA architectures so even variable latency is fine. But keeping a 4-node cluster of machines with 8 or 16 GB of RAM in synch requires a lot of bandwidth to the memory. Note that VI Architecture cluster connections don't involve the CPU much, that's the whole goal of the design.

Of course, these systems will also have multiple redundant fibre-channel storage interfaces, for the current and next generation of storage area networks. Each of these is capable of 100MB/sec, again with little or no CPU involvement once the transfers are set up. And again, the FCAL arbitration is microseconds at best, so latency is not an issue.

So Bert's statement 'Intel seems to prefer to fix the part that is not broken' is just ignorant. Intel is designing for the next generation of systems, and for the manufacturers who will be building those systems.

It's appropriate that Bert is talking about 486/33 architecture as his baseline - It probably took him 5 years to understand the design constraints of those systems. This guy needs adult supervision.