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To: Tony Viola who wrote (62772)	8/19/1998 11:52:00 AM
From: ericneu	Respond to of 186894

Tony and thread - "Tanner" info from PCMag www8.zdnet.com Intel: Tanner on Tap Details emerge on Intel's next high-end chip, due this winter. By Cade Metz August 19, 1998 -- Everyone wants to know about Tanner. Is it a beachgoer seeking sun or an antiquated British term for sixpence? Is it a craftsman who treats leather or a future Intel processor? It's all of the above-which, among PC users, begs numerous follow-up questions. Will it resemble Xeon (Intel's current workstation and server chip based on the Pentium II) or Merced (the 64-bit RISC-like chip due in the year 2000)? Will it plug in to Slot 2 or Slot M? Will it arrive this year or next? Though there's been much confusion concerning the processor's likely design, Intel recently disclosed that Tanner, due in the first quarter of 1999, is essentially a Xeon processor equipped with a new set of 3-D graphics instructions-the same instructions that will be used in the company's upcoming Katmai desktop processor. In the spring of this year, many industry publications were reporting that Tanner was a chip meant to ease the transition from Xeon, which uses the new Slot 2 connector, to Merced, which will use the upcoming "Slot M" connector. The processor would, as rumor has it, be based on the basic 32-bit architecture of Pentium II yet use a Merced connector, allowing customers to purchase Slot M motherboards well before Merced arrives, then upgrade to the 64-bit chip in the future. Though the Tanner code name was once, in all likelihood, attached to such a project, Intel now says that Tanner will offer an very different design. As it stands, Intel offers the Pentium II for desktop machines and Xeon for workstations and servers. Whereas the Pentium II-using Slot 1-houses a 512K secondary cache that runs at half the processor's clock speed, Xeon can accommodate much larger caches that run clock-for-clock with the processor. Thus, when handling the massive data sets that workstations and server chips typically handle, Xeon processors-available with 512K, 1MB, and soon 2MB caches-perform much faster than their desktop siblings. In the first quarter of next year, Intel will replace the Pentium II-at least at the high-end-with a chip code-named Katmai. This Slot 1 CPU will have the same core architecture as the Pentium II but will incorporate what Intel is calling "Katmai New Instructions"-a set of 70 instructions that, much like MMX Technology, are designed to enhance multimedia applications. Yet unlike MMX Technology-which is limited to integer-based calculations-Katmai New Instructions will deal primarily with 3-D rendering and other floating-point operations. As Intel has now disclosed, Tanner will be-in essence-a Xeon processor augmented with Katmai New Instructions. Like the Katmai desktop chip, it will arrive in the first quarter of 1999, use a 512K secondary cache, and initially run at 500 MHz. In all likelihood, it will plug into Slot 2, interface with its L2 cache at full speed, and eventually offer much larger secondary caches. Also likely to use Xeon's 450NX chip set, it should be an option for four-way servers equipped with memory subsystems as large as 2MB to 4MB. Any additional information about the Tanner is still forthcoming. Following Tanner-by at least a year-will be Merced, a RISC-like chip based on the IA-64 architecture originally developed by Hewlett-Packard and IBM. In addition to running a new brand of 64-bit software, it will natively run IA-32 code (used by the Pentium and Pentium II families) and PA-RISC software (used by Hewlett-Packard's proprietary PA-RISC chip). IA-64 will initially be used on workstations and servers but should eventually become the industry's de facto standard platform. Tanner's repositioning brings up yet another question: Will Intel offer another chip with another code name as a transition part from IA-32 to IA-64? Doubtless, the answer is no. Since Merced will run IA-32 software on its own-without software emulation or additional hardware-a transition chip is largely unnecessary. "The notion of a transition chip," says Bill Miller, director of press relations at Intel, "is a bit outdated.