SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Jim McMannis who wrote (36415)8/27/1998 10:17:00 PM
From: kash johal  Read Replies (1) | Respond to of 1572262
 
Jim,

FYI, the cost of an 8" wafer is more like $1400-1500 retail to design guys like me from folks like UMC etc. Actual manufacturing cost for AMD is likely to be close to $1K per wafer now that they have ramped volumes up.

So I think your projected costs at $35 is too high.

It seems to me that the CPU portion of AMD's biz. will be profitable.
If they can ship "hundreds of thousands" of 350's to OEMS say at $150 apiece we could be very profitable.

I fear the market tomorrow unless some big guys come out and say something positive.

Good luck everybody........I think we will need it tomorrow.

Regards,

Krash



To: Jim McMannis who wrote (36415)8/28/1998 12:53:00 AM
From: Tenchusatsu  Respond to of 1572262
 
Jim,

Tenchustsu, I'll call you Ten for short it that's OK.

Sure, it's OK with me, as long as I get to call you Jim. :-)

All right, I'll buy the argument that materials-wise, K6-2 will be $35, and Mendocino Celeron will be $51. But isn't the cost of making these chips much more than just the cost of materials? The whole picture can get very complicated. I just think your estimations grossly oversimplify the whole situation. Arguing that AMD will enjoy close to 80% profit margins because of die-size alone doesn't make any sense.

Come to think of it, AMD needs to have a smaller die-size, and not just because of the cost savings. AMD currently doesn't have the production capacity that Intel enjoys, so it has to utilize every square inch of silicon for what its worth. Thanks to economies of scale, Intel can afford to have a larger die size. That's why AMD chose a more difficult process to achieve a smaller die size. (Please correct me if I'm wrong. I feel like I could be way off-base with my argument here, and I don't want to be just another flamer, like some guy "who loves Cyrix innovations.")

By the way, I've got a friend who works for Wacker Siltronic. If you want, I can ask him the current market price for 8" wafers.