Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Gary Ng who wrote (63643)	8/31/1998 3:03:00 PM
From: Paul Engel	Read Replies (1) \| Respond to of 186894

Gary - Re: "Is the cost of Celeron 300A/333 lower than PII ?" The Mendocino/Celeron-A has a higher silicon die cost than the Pentium II die due to a larger die size (154 - 160 sq. mm.. vs. 131 sq. mm for the Pentium II). However, the Pentium II must add additional commercial L2 SRAM chips to complete the Pentium II package. This involves purchasing, inventory and sub-assembly operations, which are NOT ALL INVOLVED in the Mendocino/Celeron A (the Mendocino DOES have some sub-assembly with the initial packaging of the die and surface mount of the die/package to a circuit card along with SM resistors/capacitors - but the external SRAM packages are eliminated. Thus, the higher silicon costs are offset by the removal of the external L2 SRAM chips. Re: "18 or later .13 process which would reduce the cost for the silicon itself, the packaging of PII won't benefit from this thus would carry a relatively large fixed cost. What can be done in this area ?" My guess is that in the future, ALL L2 SRAM will be incorporated onto the CPU silicon - just as the Mendocino and Dixon today. The shrinking geometries will make this cost effective - and I suspect Intel will have some additional processing developments added to the new technologies to make the additional incremental SRAM costs smaller than they are today. After all, if AMD can make small die - albeit at lower yields - Intel should eventually figure out how to make smaller die at HIGHER yields. That is what got Intel to where it is today. Paul