SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Paul Engel who wrote (36718)9/3/1998 12:45:00 PM
From: Tenchusatsu  Read Replies (1) | Respond to of 1571259
 
The last word that I heard was that Dixon was targeted for Mobile applications. The premium ASPs for mobile Pentium IIs will offset the larger Dixon die cost.

It would be nice to compare the Dixon with an equivalent-MHz Pentium II. Some experts are saying, "It's the latency, stupid!" Well, that might change with the introduction of the prefetch instructions in 3D-Now and KNI.

It should be a little less. A straight extrapolation from the Mendocino is not quite accurate since the "overhead" circuitry associated with an SRAM does not have to be doubled if the SRAM itself is doubled.

Remember that some of the die dedicated to the L2 cache will be redundant columns in order to keep yields high. If a defect is found in one of the L2 cache columns, just disable it and rely on a different column.

My guess is that Intel will reduce the redundancy of the Dixon somewhat now that they're more comfortable with their high yields, so the die size will be less. It doesn't matter that much, though, if Dixon can be sold at a healthy premium.

Tenchusatsu