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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Ali Chen who wrote (36721)	9/3/1998 5:45:00 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 1571166

Ali, You must be too over-exited, men. The P-ii core already has a debugged (fully? Xeon?) controller for the backside L2 cache, with all IO pads on the proper side. True, but there was a redesign of the cache controller in order to add two uni-directional data buses, as opposed to one bi-directional bus. The two uni-directional buses may be easier because there doesn't have to be any turn-around cycles between a write and a read, and the two can even take place at the same time. However, even a minor change in design can still invite bugs, either pre or post-silicon. Maybe the pre-silicon validation (my current occupation, by the way) was so good that once first silicon was released, the powers-that-be decided to give the green flag. Assuming that even a EE student can just "glue an SRAM" to the chip is kind of naive. It's like saying that any EE student can just "glue two more Xeon processors" to a 2-way system in order to create your very own 4-way system. There are always some bugs which can crop up in the most convoluted of situations. BECAUSE THE EXTERNAL L2 CACHE IS DEADLOCKED at a FIXED 100 MHz! Good point. Very good point. Wrong point. Tell us why it's the wrong point. Tenchusatsu