To: Ali Chen who wrote (36729 ) 9/4/1998 2:40:00 AM From: Tenchusatsu Read Replies (1) | Respond to
Ali, ..there was a redesign of the cache controller in order to add two uni-directional data buses, as opposed to one bi-directional bus. Second, usually busses are separated inside the processor, and a special multiplexor is NEEDED to combine the two busses into a bi-directional one. It should be not a big deal to remove the extra block with obvious simplifications. Any EE graduate can do it given all the rtl files and documentation. Because the problem is not in the fixed frequency but in the ability of PII core to do several things: deferred write-backs that do not block L2 accesses. This makes the major contribution to P-II performance, although these features can be implemented in a north bridge for Socket7. Long (12-14 stages) PII pipeline also helps to decrease the cost of L1 misses and hide the high L2 access latency. This also explains why there is practically no performance difference between the full and a half-speed L2 in the P-II/PPro line.
