World's Highest Performance DSP Platform Delivers Best of Both Worlds
Two New TI DSPs Expand the World of Embedded DSP Applications by Pushing the Performance Envelope and Shattering Price/Performance Barriers
HOUSTON (Sept. 7, 1998) -- Texas Instruments (TI) today disclosed two new digital signal processors (DSPs) that raise the bar of performance for the DSP industry and shatter price/performance barriers for DSP-based embedded systems. At 2000 MIPS, the new TMS320C6202 opens doors for more efficient enterprise systems such as wireless base stations, voice-over IP gateways, remote access servers and other multichannel and multi-function communications applications that pack more channels and expanded services into each DSP subsystem. The new TMS320C6211 delivers 1200 million instructions per second (MIPS) at nearly 2 cents per MIPS. This unprecedented performance value opens possibilities for low-cost, embedded client applications, such as asynchronous digital subscriber loop (ADSL) modems and advanced imaging.
"Both of these new DSPs break past industry barriers. The 'C6202 pushes performance to 2000 MIPS or 500 million multiply accumulates (MMACS). The 'C6211 drives the 'C6000 advanced, Very-Long-Instruction-Word (VLIW) architecture down to a $25 solution," said Henry Wiechman, 'C6000 marketing manager, Texas Instruments. "Together, these demonstrate TI's commitment to 'C6000 VLIW DSP leadership at both ends of the application spectrum."
TMS320C6211: Revolutionary DSP Price/Performance
Featuring 1200 MIPS of fixed-point performance at $25 in quantities of 25,000, the 'C6211 delivers nearly two cents per MIPS for systems that require advanced signal processing but are sensitive to price. Examples include small office and home office (SOHOs) applications such as digital subscriber loop (DSL) client units, high-speed data transmission functions in switches and routers, wireless data clients, imaging, biometrics, remote medical diagnostics, automotive vehicle and drive train control, and security systems.
"A $25 DSP with 1200 MIPS is groundbreaking news for the communications industry," said Wiechman. "Using the 'C6211, DSL clients, for example, will be faster to build, easier to maintain and more affordable for both customers and service providers."
The 'C6211 is the first DSP to employ an innovative 2-level cache memory configuration which provides high performance in an extremely cost-effective solution. Small level-1 program and data caches and a larger, denser level-2 memory block make on-chip memory appear much larger to the DSP's CPU, enabling faster access with a relatively inexpensive integrated memory. Benchmarks on typical applications show that the 'C6211 achieves more than 80 percent of the performance of a 'C62x device running with all memory on-chip.
Integrated peripheral features also make the 'C6211 well suited to high-performance, cost-sensitive applications. A 32-bit external memory interface (EMIF) supports synchronous access to 1 gigabyte of off-chip memory. Enhanced direct memory access (DMA) supports faster access to mass storage and other input/output (I/O) peripherals. Two, 32-bit timers aid in design flexibility, and two multichannel buffered serial ports facilitate interface to T1/E1 and other high-speed communications media.
TMS320C6202: Pushing the Performance Envelope
With the capability of executing 2000 MIPS, or 500 MMACS, the 'C6202 propels the DSP architecture 25 percent higher in fixed-point processing performance than the groundbreaking 'C6201. A 40 percent reduction in package size means twice the MIPS per square millimeter over the earlier device. The 'C6202 also triples on-chip memory and doubles chip I/O bandwidth for faster data throughput and greater performance in the overall system.
Several key design features contribute to the enhanced performance of the 'C6202. The new DSP integrates three megabits of on-chip random access memory (RAM), tripling the memory of the 'C6201. By increasing clock speed to 250-MHz operation, processing speed increases by 25 percent. Like the 'C6211, the 'C6202 integrates two, 32-bit timers and two multichannel buffered serial ports to facilitate design.
An important new peripheral in the 'C6202 is a 32-bit asynchronous expansion bus that complements the primary, synchronous EMIF bus. The expansion bus provides a nearly glueless interface to PCI bridges and increases the interoperability of the 'C6202 to a wide variety of hosts. In addition, a glueless FIFO interface helps free up the EMIF for real-time, synchronous operation.
Power at 1.9 Watts and 40 Percent Size Reduction
The expanded 'C6000 fixed-point product line will offer designers significant savings in power consumption and package space. The 'C6211 and 'C6202 operate with typical internal power consumption of 1.9 watts. In addition, all of the 'C62x products will be offered in new, 27-millimeter, ball grid array (BGA) packages. Wireless base stations and access concentrator units will benefit from the greater channel density supported by the power and space savings.
Availability and Pricing
The new products are based on the same advanced VLIW central processing unit (CPU) core used in TI's industry-leading TMS320C6201, a product that is now sampling at a mere 2 watts. Instruction-set software compatibility with the 'C6201 allows developers to begin coding and debugging designs today that are targeted for the 'C6202 or the 'C6211.
Tools supporting the 'C6000 platform are available today. A toolset update with a simulator specifically designed for the 'C6211 is scheduled to ship in October 1998.
TI plans to sample the 'C6202 in first quarter 1999, with volume production scheduled for mid-1999. Samples of the 'C6211 are planned for second quarter 1999, with volume production scheduled for second half 1999. Pricing for the 'C6211 is expected to be US$25 each in quantities of 25,000. For the 'C6202, planned pricing is US$130 each in the same quantities. Both devices will be offered in the new, 27-mm BGA package.
For more information about these products, please visit ti.com
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