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To: dumbmoney who wrote (64841)	9/16/1998 12:29:00 AM
From: Paul Engel	Respond to of 186894

dumbmoney - Re: KNI MMX2 Thanks for the Usenet post. So far, the KNI implementation sounds real good - unlike the controversy over the original MMX (which was implemented differently in the Pentium and Pentium II CPUs). The FPU to MMX to FPU modes were wild in the original Pentium chip. I guess we'll have to wait a few more months till we know how good these KNI instructions are. But it soounds like Intel has learned some very good lessons - and th engineers were given some BIG TRANSISTOR BUDGETS! Paul

To: dumbmoney who wrote (64841)	9/16/1998 12:36:00 AM
From: Paul Engel	Read Replies (1) \| Respond to of 186894

Intel Investors - Intel Will be Implementing TWO 0.18 micron processes, not just one! Craig Barrett described the bifurcation of processes required to optimize CPUs or chip sets. Apparently, Intel is leapfrogging their OLD methodology and are now designing their new integrated chip set (Whitney) in a 0.18 micron process but it requires a denser set of metallization design rules. Accordingly, Intel seems to be developing a modified 0.18 micron process with thinner metal layers (probably tighter metal pitches as well) for the chip set/graphics combination. That is really getting aggressive ! Here's the article describing the two processes. Paul {==================================} edtn.com Top Technology Story: EE Times Intel foresees fork in its process road map By Rick Boyd-Merritt PALM SPRINGS - Intel Corp. is positioning itself to put as much of its manufacturing clout behind low-cost, highly integrated peripheral chips as it traditionally has placed on its high-end microprocessors. In a small group meeting here before delivering a keynote address at its Intel Developer's Forum, Intel president and chief executive officer Craig Barrett revealed the company is currently ramping up in tandem two "mainstream" 0.18-micron logic processes - one that would be geared for the needs of its high-end processors and another tailored to the requirements of its core logic, graphics and embedded semiconductors. "In the past, we developed one logic process for our high-end microprocessors and all our other chips used that process as it became trailing-edge technology," Barrett said in a Monday night meeting with a small group of editors. "But now we are chunking out a lot of i740 [graphics controllers] and core logic and we want them to have the smallest die size possible." While both logic processes would use the same basic equipment set, they would diverge in design rules, he added. The processor technology would be geared toward fast switching of large signal loads while the peripheral-chip process would aim at thinner metalization layers, he said. The process-technology divergence first emerged in the 0.25-micron generation, in which much of Intel's Pentium II family is currently made, Barrett added. But with the 0.18-micron generation set to be in volume production by mid-1999, the two processes for the first time would be distinctly defined from the start. The new peripheral process could be a sign Intel is ready to put its considerable manufacturing muscle behind integrated processors that would compete with the likes of National Semiconductor's "PC-on-a-chip," which is expected to ship next June. Intel plans to ship a merged core-logic/graphics chip set next year, dubbed Whitney, and analysts have speculated that beyond the 0.18-micron generation, it would make sense to integrate Intel's Celeron processors with north bridge core logic and graphics. "You are definitely going to see integrated computing at the low end with graphics, processors and so forth," Barrett said. "And you want to be as cost-effective as possible at that low end." The process-technology divergence comes at a time when much of the industry is seeing a significant slump, in part attributed to the Asian financial crisis and slack PC demand early this year. Responding to the downturn, Intel cut its capital-expenditure plans from about $5 billion to about $4.6 billion this year, mainly through delaying plans to start a 300-mm, 0.13-micron wafer fab in the Fort Worth, Texas area, Barrett said. "Basically, the whole industry has decided to push off 300 mm until the 2002-2003 time frame," Barrett added. "We aren't going to be the first ones to pioneer it, and it's not clear at this point who is." Despite the downturn, Intel reported last week it expects its third-quarter revenues to be up 8 to 10 percent over second-quarter revenues. It attributed the uptick to increasing PC demand in North America and Europe.

To: dumbmoney who wrote (64841)	9/16/1998 1:16:00 AM
From: Tenchusatsu	Respond to of 186894

The Katmai has 8 128-bit MMX2 registers usable as 4x32bit fp each. They are not aliased to the normal fp or MMX registers. So the size of the architected register file just went up by a huge factor, eh? Looks like the predictions made by Microprocessor Report were true, and that Intel now has more registers to play with. I had a hard time believing it at first, because this would require one massive transistor budget. Unlike 3D-Now, whose complexity was kept to a minimum to reduce time to market, it seems that KNI is an huge step for the x86 instruction set. The advantage is that you can do MMX2 in parallel with MMX or fp work, This is great news for the Xeon line. KNI will give Intel some inroads into the graphics workstation market once Tanner is released. I wonder how many KNI instructions can be executed at one time. K6-2 can do two 3D-Now instructions simultaneously. Did AMD get this one wrong for 3D-Now? Hard to say. 3D-Now is adequate for game acceleration, where speed is more important than robust functionality. Either AMD and its supporters will be saying that 3D-Now is good enough for most people, or AMD has some improvements lined up for 3D-Now. If it's the latter, I wonder what it will be called. 3D-Now-2? 3D-Now-The-Sequel? K8? There are conditional move commands, conversion functions for MMX and FP, memory-streaming (cache control), distance calculation and min-max commands. From a system perspective, those memory-streaming cache control commands are perhaps the most useful, since it sounds like they'll allow the processor to work around the huge latencies of the L2 cache and SDRAM/RDRAM. Then bandwidth, not latency, becomes the limiting factor, and we all know what bandwidth RDRAM promises. Thanks for the scoop, dumbmoney. Tenchusatsu