To: Tony Viola who wrote (24388 ) 9/19/1998 10:01:00 AM From: Katherine Derbyshire Read Replies (2) | Respond to of 70976
>> In fact, it also came out this week that Intel will have TWO 0.18 micron processes, one for processors and one for peripheral chips. Separation of 0.18 lines at Intel must mean more equipment is required by them. Anyone know for sure?<< Not really. Their capacity needs would require more than one 0.18 micron fab anyway, so having two processes just means that the two (or more ) fabs aren't doing the exact same thing. >>Barrett used his talk as a platform to convince developers that the copper interconnect and Silicon-on-Insulator (SOI) processes used by Motorola, IBM and other semiconductor makers are not the way to increasing performance within a microprocessor. Instead, Barrett said that Intel will concentrate first upon increasing the speed of the transistors within the chip, moving to the faster copper interconnect process only in its 0.13-micron generation. << A fairly famous graph that I haven't been able to find online anywhere shows the relative importance of interconnect speed and transistor speed. With aluminum and oxide dielectrics, interconnect delays dominate the total after the 0.25 micron generation. That is, circuit delay goes up--way up--even as gate speed improves. Since Barrett is almost certainly aware of this paper (it was written by an Intel scientist and has been quoted in three or four places that I know of), I suspect there were subtleties in his presentation that didn't make it into the article. For anyone interested, the original reference is: Bohr, Mark T., "Interconnect Scaling--The Real Limiter to High Performance ULSI," Proceedings of the 1995 IEEE International Electron Devices Meeting, 1995, pp241-242. The graph is quoted in the SIA Roadmap as well. I think the roadmap is online at the SIA site (www.semichips.org), but I don't have time to go hunting for the graph. Any volunteers? Katherine