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To: AJBurl who wrote (9612)	9/17/1998 8:11:00 PM
From: SemiBull	Read Replies (1) \| Respond to of 11555

IBM Leads Way With Super Speedy SRAM By Andrew MacLellan Promising a huge leap in workstation and server memory performance, IBM Microelectronics has introduced an 8-Mbit SRAM with a clock rate of up to 600-MHz. By running data on both edges of the chip clock, the double-data-rate SRAM device offers twice the speed of today's most advanced SRAM chips, according to IBM, Fishkill, N.Y. The IC's 8-Mbit density represents another substantial advance, and will replace existing 4-Mbit devices in many systems, the company said. "This 8-Mbit high-performance SRAM will enable the next generation of higher performance workstation systems," said Kevin Carswell, director of IBM memory products. While the DDR specification has been around for some time, other semiconductor vendors pursuing the technology, such as Samsung, Sony and Motorola, are not expected to match IBM's speed or density until the first quarter of 1999, according to Jesse O. Huffman, an analyst with In-Stat Inc., in Cameron Park, Calif. "As of today, IBM is the first in the marketplace to announce," Huffman said. "They're ahead of the pack." Samsung, has however, just introduced a new DDR SGRAM. IBM's new chips will generally be used in up-market RISC-based UNIX workstations and servers as a replacement for late-write SRAM. However, DDR SRAM will probably not appear in so called Wintel-based platforms, because Intel workstations and servers driven by Pentium chips generally have a wider ratio between the processor clock and memory, according to IBM. But in high-end UNIX systems, where multiple processors may each use up to 4 Mbytes of SRAM cache, system performance improvement could be dramatic, according to Huffman. "This is an area where more SRAM cache is definitely a bandwidth enhancer," he said. The IBM roll out is also expected to herald a transition to 8-Mbyte-per-processor cache configurations, a switch the industry has been preparing for for some time. A consortium of workstation/server vendors and SRAM suppliers has already sketched out a roadmap that will take them through 16-Mbit densities in coming years, moving per-processor cache capacities from 2 and 4 Mbytes to 8 Mbytes and beyond. One drawback to the DDR architecture is that processors will have to modify their cache control logic to recognize the double-data-rate signal, according to Roger Verhelst, SRAM marketing and applications manager for IBM. "With normal cache SRAM, for each processor clock cycle we can deliver one piece of data from RAM, whereas with double-data you've got one piece of data on the rising edge and one piece on the falling edge of the clock," Verhelst said. Even so, DDR SRAM is backward compatible to 1- and 4-Mbit late-write SRAM, and without making any changes to the control logic will deliver up to 330-MHz access speeds, according to IBM. While the faster SRAM will help OEMs increase densities and performance, it will likely do little for the PC cache market, which is currently using chips in the 133- to 166-MHz range. Additionally the breakthrough will prove overkill in most communications markets, which are only just beginning to clamor for 200-MHz performance. IBM's DDR SRAMs were introduced in both 4- and 8-Mbit densities and are manufactured on the company's 0.25-micron CMOS 6X process and packaged in industry standard PBGA packages. Prices vary according to application, but IBM said the 4-Mbit 600-MHz device will carry about a 10% premium over single-data rate SRAM of the same density. The higher density 8-Mbit DDR part will carry a small additional premium. Production quantities of the new SRAMs are available.