Tony, article...Emulator sheds early light on Merced software
September 22, 1998
ELECTRONIC ENGINEERING TIMES : Palm Springs, Calif. - Intel Corp. last week demonstrated the first Merced software ever booted up in public, showcasing a 64-bit version of Windows NT in a presentation at the Intel Developer's Forum, here. The demo ran on a sophisticated software emulator that mimics the complete Merced instruction set, the chip's firmware-processor interface and its multiprocessing interrupts.
"We have major operating systems booting and running on this presilicon development environment, which is a high-speed software emulator for [Merced] that runs on an IA-32 host," said Rumi Zahir, an Intel senior architect. "It simulates an entire IA-64 platform that includes multiple processors and the standard platform devices, and it provides multiprocessor simulation capabilities."
Separately, Intel sources revealed several new details about some of Merced's internal features, including registers intended to enable advanced code optimization. New information on Katmai, Intel's advanced 32-bit processor, also came to light.
Because samples of actual Merced silicon won't be available before mid-1999, Intel is providing its emulator to the software community in hopes of sparking the development of 64-bit software. "When Merced is ready, we can't just ship silicon. We understand that we need to have a fully functional system with all the software components," said Zahir. "Because it models more than just the CPU, this [emulator] environment enables developers to do operating-system and application porting, as well as development of firmware and BIOS code."
Though the emulator isn't publicly available, Intel has provided it under tight non-disclosure restrictions to a host of top-flight software houses. Along with the new version of Windows NT, other 64-bit OS implementations currently in the works for Merced are an IA-64 release of HP-UX from Hewlett-Packard; Unixware from SCO; Irix from Silicon Graphics; Modesto, a 64-bit version of Netware, from Novell; Solaris from Sun; and Unix from Digital.
According to Intel, some of those Unix releases are already running on the Merced emulator. "We have multiple operating systems and multiple apps up and booting," said Hemant Dhulla, Intel's IA-64 marketing manager. Apps include a large commercial database, he said.
For developers, the availability of Intel's emulator-along with related tools such as compilers, debuggers and performance-tuning software-is shedding new light on the tough task of creating IA-64 applications. Of crucial importance is how to make proper use of Merced's complex code-optimization features-notably, predication and speculation. Also at issue is how to proceed with debugging.
Developing software for Merced won't be as cut-and-dried as programming for previous X86 generations used to be, because the IA-64 architecture ushers in a new kind of cooperation between on-chip hardware and compiler. With a heritage drawn from very-long-instruction-word (VLIW) architectures, Merced will contain a large number of parallel execution units. In exchange, Merced's compiler must organize programs into instruction streams that can be simultaneously executed.
To obtain those streams, the compiler will rely heavily on predication, which removes unnecessary branches from a program, and speculation, which masks memory latency by executing load instructions as early as possible.
Few companies have the resources to create a compiler smart enough to implement such techniques. That's why Intel has written its own compiler back end (the portion that performs the final, IA-64 code generation) and is providing it to key software houses, including compiler vendors Metaware Inc. (Santa Cruz, Calif.) and Edinburgh Portable Compilers Ltd. in Scotland. Microsoft is also developing compilers for Merced.
One company that does have sufficient compiler smarts is Hewlett-Packard, Intel's partner in defining the IA-64 architecture. HP is developing its own compiler and recently spearheaded the release of an academic compiler, called Trimaran, aimed at university researchers studying Merced-like architectures (see Sept. 7, page 41).
Because Merced's performance depends in large measure on how adeptly compilers optimize code, one of the most interesting questions kicking around has been: How much better is Merced's performance when it is able to take advantage of speculation and predication?
"There's no blanket answer," said Intel's Zahir. "Workloads that fit in the processor caches might run reasonably well [without the features]. Larger workloads like databases tend to benefit substantially by using speculation or predication, because [these features] can manage the memory latency much better."
The features can be turned on or off by commands provided to the compiler. This gives developers a safety margin when they venture into uncharted IA-64 territory by allowing them to incrementally turn on more advanced features as their code passes muster.
"That is a key capability the [emulator] gives you," Zahir said. "You can do a quick-and-dirty recompile and get the program to work. Then, in a second round, you can turn on some of the IA-64 compiler switches and see what happens."
To boost performance further, Intel added hooks to the latest version of its tuning tool, Vtune 3.0, to let it work with Merced.
Still, debugging IA-64 apps won't be a cakewalk. Compilers that use code-optimization features end up rearranging programs so much that it's tough to map the correspondence between final machine code and the original high-level program.
"Debugging of optimized code has been a problem all along. I don't think there's anything new here," said Zahir. "A lot of debugging has to happen at lower optimization levels, until you have a level of confidence your code is doing what you expect it to do. Then the compiler can step in and start optimizing."
Intel is also adding features in hardware to help hardware and software developers optimize performance, including a series of on-chip performance-monitoring registers. Such registers have been a part of every CPU since Pentium. But in Merced, Intel adds an unprecedented number of new counters.
The result is "far greater resolution into which pieces of the code are causing performance issues," said Zahir. "An address-range check facility allows you to zoom in on particular pieces of the code." Another register, Merced's "op-code matcher," enables the viewing of specific types of instructions.
Developers creating 64-bit apps with help from an emulator may wonder how such code will work under real-world timing conditions. According to Intel, the Merced emulator is "one for one" in terms of instruction-set emulation. "It's a functional emulator that does exactly what the hardware will do," Zahir said.
Even with timing-dependent items, "the amount of effort you need to put in will be an order of magnitude less, if you've made things work on the emulator, " Zahir claimed.
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