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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Paul Engel who wrote (37491)	9/26/1998 11:52:00 AM
From: Elmer	Read Replies (1) \| Respond to of 1572060

Re: "Why would a single processor snoop its own bus - unless it wasn't aware of what it was doing ?" I/O writes to memory (ie PCI) can force a snoop so the L1/L2 can stay current. EP

To: Paul Engel who wrote (37491)	9/28/1998 2:00:00 PM
From: Scumbria	Read Replies (1) \| Respond to of 1572060

Why would a single processor snoop its own bus - unless it wasn't aware of what it was doing ? Paul, MP busses have extra latency to allow for the possibility of snoops. The must provide the ability to invalidate data after a remote snoop hit, even if there is no such activity occurring. If you want to build a minimum latency single processor bus, you will not implement an MP protocol. A good example of this is the Cyrix MediaGX, which has extremely low dram latencies. Scumbria