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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Fred Fahmy who wrote (65717)	10/1/1998 9:57:00 PM
From: Paul Engel	Read Replies (2) \| Respond to of 186894

Fred and Intel Investors - Intel has Achieved a Major Technology Milestone, but the ever-vigilant media press seems to have completely missed it. A few days ago, Hewlett Packard announced the availability of a new PA-RISC processor, the PA-8500. This CPU is a a milestone in that it incorporates a HUGE 1.5 Million Bytes of Level Cache, and consumes 140 million transistors. The ever vigilant press seems to have not inquired as to HP's technical expertise in developing and manufacturing such a device - reportedly on a 0.25 micron process. It has come to my attention that HP, in fact, did not develop such a wafer fab process. Instead, HP designed this monster CPU using Intel's P856 design rules - and Intel is the manufacturer of the PA-8500 - for HP's exclusive use. HO, of course, was the circuit designer. The significance of this is that Intel's process technology and manufacturing yields are now in such a state that these HUGE, MONSTER chips are economically feasible to manufacture. By the way - I am not certain of this, but the die size could be as large as 488 sq. mm. and approximately 48 possible die sites should be available on a 200 mm wafer. The 1.5 MegaBytes of memory should use up only 72 million transistors - so I am speculating that a total of 3 MegaBytes of Level 1 SRAM cache may be available on the - and HP could "double" the cache size if all SRAM cells were completely functional. My guess is that the cache is partitioned into TWO halves and the circuit allows either cache to be used in case the second was is not completely functional. Intel's SRAM redundancy architecture is also most likely being put to use as well. Note in the first article below that HP and Intel pulled off this development FIVE (5) months ahead of schedule ! This capability has been alluded to in last weeks Intel Developer's Forum and Intel should be busy incorporating up to 2 MegABytes of cache on the upcoming 0.18 micron Cascades - due next year. This will happen. The HP disclosure articles are listed below. Paul {==============================} HP Rolls Out Processor Upgrade By Edward F. Moltzen, Computer Reseller News Sep 29, 1998 (2:17 PM) URL: techweb.com Hewlett-Packard, which has watched as rivals Intel and IBM have rolled out several critical upgrades to their microprocessor lines, was expected to roll out an upgrade of its own Monday. The Palo Alto, Calif.-based computer maker (company profile) said it will offer a board upgrade to its PA-8500 processor for workstations to include more cache, transistors, and greater performance. HP executives said the upgrade board will be priced at $7,990, and the company will begin taking orders Sept. 29. The processor upgrades are being made available as part of a package on HP's Visualize Model C200 and Visualize Model C240 Unix-based workstations. "We're just about to begin the transition of our product line to the 8500," said Barry Crume, product marketing manager for HP's workstation-systems division. While the upgrade to the HP processor will support binary codes developed on previous chip architectures, it will offer new technology that will boost performance, he said. "It does make one major breakthrough," Crume said. "It uses a large, on-chip cache. There is 1.5 [megabytes] of cache memory located physically on the chip." The 8500 upgrade will register a clock speed of close to 360 MHz, Crume said. By employing 0.25-micron architecture, HP was able to contain 140 million transistors on the chip, compared with about 10 million it would otherwise be able to build there, he said. Crume said the processor upgrade is about five months ahead of schedule. The processor upgrades for HP come almost a year after IBM Microelectronics said it had perfected the so-called copper chip technology that would offer major processing performance boosts and months after the computer giant said it had developed a new manufacturing process -- Silicon on Insulator -- that would also produce performance enhancements. Already this year, Intel has begun shipping its Xeon processor, which offers a clock speed of 400 MHz, and has dual-processing capabilities in workstations. However, in addition to beating its timetable for delivering the technology, HP said it has made advancements in making it easier to upgrade systems. Once the workstations are upgraded to HP-UX 10.20, a tray is removed from the back of the chassis, the memory system is moved to the new PA-8500 processor board, the new board is plugged into the tray, and the tray is reinserted into the system. The process is supposed to take several minutes, HP said. {=================================} hp.com PA-8500: The Continuing Evolution of the PA-8000 Family Gregg Lesartre Doug Hunt Hewlett-Packard Company 3404 East Harmony Road, MS 55 Fort Collins, Colorado 80525-9599 Abstract The PA-8500 is the newest member of the PA-RISC family of processors. The design is based on the PA-8000 and PA-8200 processors, but is implemented in a 0.25 micron process. The new process allows the large first level caches to be moved on-chip so that the frequency can be boosted without the need to add tightly-coupled second level caches. Improvements have also been made in the branch prediction hardware to allow a single branch prediction structure to take advantage of static and dynamic branch prediction techniques seamlessly. These improvements and others will allow the PA-8500 to deliver industry-leading application performance. 1. Introduction The PA-8500 processor, now under development at Hewlett-Packard's Engineering Systems Lab in Ft. Collins, Colorado, is the latest addition to the PA-RISC[1,2] family of processors. The design goals of the development project are to deliver a processor which will: Lead the industry in application performance. Provide full binary compatibility with all existing PA-RISC binaries. Deliver maximum performance on binaries tuned for the PA-8000 and PA-8200. Interface to the Runway system bus.