Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Yousef who wrote (37916)	10/2/1998 12:39:00 AM
From: Maxwell	Read Replies (2) \| Respond to of 1571884

Yousef: Please indulge us with Intel 0.18um process while we are awaiting for AMD Q3 earnings. What speed is Coppermine expected to run? Vcc=2.0V or 1.8V or less? What is Leff and Idsat for n and p channel. Also tell us the M1, M2, and M3 linewidths and pitches. Will vias be anchored or unlanded? Will Intel use IMP Ti or any other metal for contact fill? How many metal layers and will it use C4? What is maximum speed Intel can achieve on the 0.18um? How much shrinkage Intel expect to get the CeleonA at 0.18um? How about some speed spread within a lot of 20 wafers? Maxwell