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To: REH who wrote (7772)10/2/1998 6:29:00 PM
From: REH  Respond to of 93625
 
Molex Boosts Xeon Connector Contacts, Speed

Oct 02, 1998 (Tech Web - CMP via COMTEX) -- The Slot 2 connectors Molex
will roll out next week for Intel's Pentium II Xeon processor will
employ novel techniques to satisfy requirements set by Intel and Molex
when they began working together in 1994. The connectors borrow
circuit-board techniques to handle higher speeds while increasing
contact density.

The HiSpec card edge connectors are designed for servers and other
high-end applications that require Xeon, which was introduced in June.
The connector itself is only slightly larger than the Slot 1 connector
found on many desktop systems, but it has 110 extra contacts and can
handle signals that are more than twice as fast. Some of the techniques
implemented on the Slot 2 connector are already being employed in other
Molex connectors.

Molex and Intel worked for four years to get more lines running at
higher frequencies. The challenge was heightened because the
characteristics were to be achieved without making manufacturing more
complex for Molex or for the system houses and contract manufacturers
that will use it.

Lofty Goals "We had plenty of goals: We had to hit Intel's speed and
density requirements, and we had to carry enough power for future
generations of the chip, which will draw more power and have more
simultaneous switching," said Jim McGrath, strategic product manager at
the Computer Strategic Business unit of Molex, in Lisle, Ill. "This
couldn't use new manufacturing techniques. It had to hit the
manufacturing floors at our plants and our customers and be running
right away."

It took an international team of Molex designers to come up with the
complete system for the interconnection system. Although Santa Clara,
Calif.-based Intel was setting the guidelines, Molex was able to adjust
them so installed costs for the connector could be decreased.

"Intel originally wanted a 0.025-inch pinch, but we ended up with a
0.030-inch pitch," McGrath said. "We said 0.025 would be difficult at
our end, but it would be a nightmare at theirs. In the module, there
would be a much greater chance of solder-bridging, and the ability to
route to the contacts would be much harder at the finer pitch. They
might have had to add substrate layers to route at that density, and
that would add to costs."

The connector has several more pins than its desktop counterpart. The
Slot 2 connector puts 330 card edge contacts in a housing that is 5.66
inches long, while the Slot 1 connectors found on desktops have 242
contacts in 5.23 inches, with a pin pitch of 1 millimeter.

Molex's Goal-Reaching Strategy To meet the goal, Molex came up with the
idea of staggering the pads. That allows a 0.030-inch pitch for the
edge contacts while providing pad widths of 0.032 inches. That matches
the tolerances of conventional PCI connections, which helps the
connectors to fit existing production techniques.

The combination of density and high performance forced Molex to come up
with a novel concept it calls complementary contacts. Metal contacts
are the same size in most connectors, but Molex has made the power and
ground contacts much larger than those that carry signals.

The larger surfaces look and act more like ground planes. Use of the
smaller contacts for signals lets Molex put more contacts in a given
amount of space. The signal lines employ microstrip and stripline
techniques like those used on circuit boards to provide high speeds.

The microstrip and stripline techniques are complemented by a number of
power/ground contacts. Many high-speed connectors employ a 1-to-1 ratio
of ground and signal lines to minimize crosstalk, but Molex and Intel
couldn't afford the space required for that many contacts.

Instead, they employed larger contacts for power and ground signals,
and placed two smaller ones between each pair of ground connectors.
While grounding is important, power-handling is equally critical for
future products.

"As we see continued drops in voltage, wattage doesn't change, so
current goes up," McGrath said. "In processor applications, it's not
just the processor, but the Level 2 cache runs as fast as the chip, so
you need more current."

Although Molex is prepared to license the technology to other connector
makers, it is a sole source supplier for Intel, and no other
manufacturer has signed on as yet. The company said it does not expect
that to be a problem, however.

"We have 50 percent more capacity than the highest-demand estimate,"
McGrath said. "We're probably OK for three years."

Other Molex groups are already adopting the complementary contacts
technology. Molex is also preparing to introduce connectors for Rambus
memory modules, and will use multisized contacts in that product. Other
Molex operations are also exploring possible uses for the contacts.





To: REH who wrote (7772)10/3/1998 8:02:00 AM
From: REH  Respond to of 93625
 
Chip-set support improves VCM's odds vs. Rambus -- NEC alters race to faster PC memory

Oct. 02, 1998 (Electronic Engineering Times - CMP via COMTEX) -- Tokyo
- NEC Corp. has garnered support for its virtual-channel-memory SDRAMs
from three of Taiwan's top PC-core-logic makers, and the first
motherboard prototypes supporting the new architecture are in the
offing. The development poses a threat at the low end to the plans of
Intel Corp. and Rambus Inc. to drive Direct Rambus as the PC memory of
choice starting next year.

Forthcoming chip sets from Acer Laboratories Inc., Silicon Integrated
Systems Corp. and Via Technologies Inc. give PC makers an opportunity
to boost memory-bandwidth performance beyond the current PC-100 SDRAM
spec and to do so ahead of Intel's planned introduction of its first
Direct Rambus DRAM chip set, Camino, slated for next year. The chip-set
makers are gearing up to deliver products that serve both Socket 7 and
Slot 1 processors from Intel and its competitors.

At least two of the Taiwanese companies will support VCM in chip sets
with integrated 2-D/3-D graphics capability for Slot 1 processors
starting this year. That silicon will likely fuel a battle in the
market for low-cost but high-performance systems.

Support from the core-logic makers comes on the heels of another VCM
deal, in which NEC won support for its approach from Siemens (see Sept.
14, page 1). Sources said Micron Technology is also investigating
VCM-based DRAM manufacture, but Micron executives were not available
for comment by press time.

"VCM doesn't really jeopardize Intel's road map for delivering Direct
RDRAMs over the next few years, but if Direct RDRAMs come out with too
high a price, VCM has a window of opportunity at the low end," said
Steven Przybylski, a principal of the Verdande Group (San Jose,
Calif.). "The question is: How long is that window open, and will the
Direct RDRAM pricing be high enough for NEC to capitalize on it?"

Przybylski said he does expect Direct RDRAMs to carry a price premium
that keeps their volumes modest and confined to high-end PCs in 1999.
But he added that NEC needs broader support among DRAM makers for its
VCM approach before it will have the clout to drive the technology into
the mainstream.

Chip-set support is a "necessary but not sufficient condition" for
success, he said. "Having four DRAM backers would make VCM a viable
alternative."

And getting that support won't be easy. "DRAM makers have a lot on
their plate right now," said Przybylski. "Direct RDRAMs are coming up
slowly. They need to shrink their PC-100 SDRAMs to reach profitability,
and their ability to focus on a new architecture is fairly limited at
this point."

Intel is hewing to its position of promoting faster Direct Rambus
DRAM across all platforms, and has publicly discouraged fragmentation
of the DRAM market. NEC faces difficulty in persuading top-tier DRAM
vendors to become second sources for the chips as they focus much of
their development efforts on Direct Rambus.

One difficulty may be that virtual-channel SDRAMs have come late to
the high-bandwidth DRAM game. NEC announced the technology late in
1997-more than a year after Intel and Rambus had started working on the
Direct Rambus interface. With many of the top-tier DRAM vendors focused
on Direct Rambus, NEC may be hard-pressed to sign high-profile second
sources.

Indeed, Samsung said it has no plans to add virtual-channel SDRAMs to
its road map, and Toshiba said it is concentrating on Direct Rambus.
Even NEC recently said it will accelerate its Direct Rambus production
schedule to 1 million units per month by mid-1999, though the company
estimates that virtual-channel DRAMs will account for nearly 40 percent
of its output by the end of 1999, compared with about 10 percent for
Direct Rambus.

Having support from all the major alternate PC-chip-set suppliers
could give DRAM suppliers some assurance that there will be sockets
available for the new memory type, said Misao Higuchi, NEC's manager of
memory engineering. "Getting second sources is a chicken-and-egg
problem," he said.

The shift to VCM could be somewhat troublesome for memory makers
because it involves incorporating a new DRAM core and a new mask set,
said Przybylski. By contrast, adding the VCM interface logic to a chip
set's so-called north bridge is a low-risk proposition because chip-set
makers can readily design their memory controllers to support
extended-data-out (EDO) DRAM, SDRAM and virtual-channel SDRAM. That is
not the case with more advanced memory devices, such as Direct RDRAMs,
which require a special protocol-based interface on both the DRAM and
the memory controller.

And because virtual-channel SDRAM is an open standard, chip-set
vendors do not have to purchase a license or pay royalties to support
the faster memory architecture, as they must for Rambus.

Easier to adopt

Motherboard makers also would find it easy to adopt VCM compared with
Rambus or double-data-rate (DDR) SDRAM. Aside from minor tweaks to the
DRAM controller and the BIOS, VCM uses the same circuit boards and
dual-in-line memory modules (DIMMs) employed for SDRAMs.

"DDR and Direct Rambus will require a change in the motherboard
design," said Higuchi of NEC. "Also, one big concern with DDR and
Direct Rambus is power consumption. Direct Rambus requires you to have
a heat sink on the module."

Virtual-channel memory is a variation of SDRAM incorporating 16
channels of independent cache lines to filter out page misses. The
scheme is said to slash DRAM latency during initial access. It also
requires smaller I/O interfaces and sense amplifiers, cutting power
consumption by 30 percent over conventional SDRAM running at the same
frequency, according to NEC.

VCM won't provide the same high bandwidth as Direct Rambus, which
will move data at 1.6 Gbytes/second. What VCM will provide is a step up
from the PC-100 DRAMs that are now moving into mass-production. NEC
said virtual-channel DRAMs are specified to run at 133 MHz with a
two-clock CAS latency. Peak bandwidth is 1 Gbyte/s, vs. 700 to 800
Mbytes/s for PC-100 devices.

What's more, virtual-channel DRAMs provide about 30 percent higher
bandwidth efficiency than PC-100s. All told, the memory technology will
boost total system performance between 1.5x and 2x over existing
technologies, according to NEC.

Przybylski said that he did not have specific performance figures for
VCM but that he thinks the performance boost over standard SDRAMs could
be minor for general-purpose PC applications.

The idea of a 133-MHz SDRAM is not new. In fact, Intel last year
admitted that it had considered formulating a specification for such a
device and had alerted DRAM vendors with a preliminary spec. But aside
from a proposal earlier this year that would allow PC-100 SDRAMs to be
placed on a Rambus RIMM module, it appears Intel is staying true to its
plan to guide the industry from PC-100 SDRAMs to Direct Rambus. That
leaves VCM out in the cold with Intel-which has 70 percent of the
chip-set market.

Talks with Intel

"Intel now is officially focused on Direct Rambus from the high end
to the low end," Higuchi said. "But if a backup solution is needed from
the midrange to the low end, VCM is one solution. There are some
engineering groups at Intel that we have had discussions with, but it's
a difficult situation."

Via appears to be the first chip-set maker to have adopted the new
memory technology. The company has started sampling a version of its
MVP3 Socket-7 chip set that is retrofitted to support VCM SDRAMs, and
plans call for the upcoming MVP4 Socket 7 chip set, with integrated
2-D/3-D functions (including a setup engine), to support
virtual-channel DRAMs up to100 MHz. Via is due to sample its Apollo Pro
Slot 1 chip set, with an integrated 2-D/3-D GUI that will support
virtual-channel SDRAM up to 133 MHz.

A spokesman at Via said the company has samples of VCM-compatible
chip sets for both Socket 7- and Slot 1-based motherboards.

Acer, meanwhile, plans to sample its Aladdin-Pro III chip set by
November, with production quantities scheduled for the first quarter.
The M1631 north-bridge chip is a Slot 1 device that will interface to
Intel's Pentium II and Mendocino processors. It supports
virtual-channel SDRAM up to 100 MHz, according to an Acer road map
provided by NEC.

"We will definitely offer a VCM-compatible product," said Acer vice
president C.L. Tsai. "We are interested in VCM for four reasons. First,
our chip sets already supported the multibanking that is central to
VCM. Second, VCM is basically just a superset of SDRAM, so we only
needed to add on some command protocols. Third, VCM offers higher
performance, since it can run SDRAM at 133 MHz; and finally, VCM is
free."

Silicon Integrated Systems' road map was unavailable, but the company
plans to introduce its first virtual-channel-SDRAM-enabled chip set
early next year, according to NEC.

The Taiwanese move into Slot 1 core logic may prompt
intellectual-property clashes with Intel, which tightly holds the
rights to use the P6 bus architecture behind Slot 1. Via, which will
begin commercially producing its Slot 1-compatible Apollo Pro 1 in
November, believes it has short-term IP protection "because we will use
IBM to fab the Apollo Pro for us," said the spokesman. "We are also
negotiating with Intel for our own Slot 1 license."

Silicon Integrated Systems is taking a somewhat different tack. "We
have spent over two years developing our Pentium II product, the SiS
620," said vice president Shing Wong. "Much of the effort was making
sure we did not infringe on any of Intel's IP. We also have been
working closely with Intel to understand the possibility of having an
official technology license from Intel."

Advanced Micro Devices (Sunnyvale, Calif.) is offering chip-set
makers an alternative to the Socket-7 and Slot-1 plugs with its 100-MHz
Super7. AMD touts Super7 as an "open" standard, an appeal that has
garnered support in Taiwan and elsewhere. As many as 40
Super7-compliant motherboards have been developed, largely by Taiwanese
companies, and 100-MHz Super7 systems are appearing from IBM Corp. and
others.

A potent combination may be developing: AMD's K6-2, or the
Super7-compliant Cyrix MII processors from National Semiconductor's
Cyrix division (Dallas), with VCM-SDRAMs, using core logic and
motherboards from Taiwan's chip-set and motherboard vendors.

AMD wasn't ready to talk about its position on VCM last week, a
spokesman said.

Moreover, several graphics and chip-set makers are working on
combining 2-D/3-D graphics capabilities with system-core logic for
desktops. Trident Microsystems (Mountain View, Calif.) is working with
Acer and Via to deliver its Monterey 3-D graphics functionality on the
same die as system logic from Via and Acer. -Mark Carroll, David
Lammers and Rick Boyd-Merritt contributed to this report.