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To: gnuman who wrote (65746)	10/2/1998 2:16:00 PM
From: Jim McMannis	Read Replies (1) \| Respond to of 186894

Gene, Thanks. Looks like Xeon is off to a rocky start. The part about a 5% speed gain from a Pentium 200 was very interesting. Jim

To: gnuman who wrote (65746)	10/2/1998 2:55:00 PM
From: Tenchusatsu	Respond to of 186894

Gene, regarding the PC Week Xeon article. There were a few little fuzzy points in the article that made me wonder. I'll point out three of them: "I've seen about a 5 percent increase between a Pentium II 200 and a [Xeon]," There is no such thing as a Pentium II 200. Perhaps the guy meant a Pentium Pro 200, but I wonder what programs he was running which led him to the conclusion of the mediocre 5 percent increase. Obviously MS Word is not going to show any noticeable improvement. But in heavy data-crunching apps, benchmarks prove that Xeon is twice as powerful as Pentium Pro. According to sources at several OEMs, Intel has concluded that the 450MHz Xeon will perform about the same as the 400MHz Xeon running typical workstation programs. Once again, what are the "typical workstation programs?" Benchmarks would be nice. Intel confirms a bug in the 450NX chip set that delays Xeon-based servers by six to eight weeks. Company officially announces Xeon, but server OEMs can't ship Xeon products because of 450NX bug. No, it wasn't a 450NX bug, it was actually a Xeon bug which only showed up when used in a 4-way configuration on a 450NX chipset. Intel themselves made this clear. The 2-way config did not exhibit this problem. The article does make excellent points about the unsold Xeon recall and the subsequent delays, as well as the questionable marketability of the 450 MHz speed and the larger L2 caches. However, the inaccuracies in the article makes me wonder whether the writers are grasping at straws in their efforts to paint a one-sided negative picture of Xeon. Tenchusatsu

To: gnuman who wrote (65746)	10/4/1998 6:53:00 PM
From: VICTORIA GATE, MD	Read Replies (1) \| Respond to of 186894

October 05, 1998, Issue: 1029 Section: Systems & Software -------------------------------------------------------------------------------- Internal layout of Intel's Merced comes to light Alexander Wolfe Santa Clara, Calif. - The first detailed block diagram of Intel Corp.'s upcoming Merced microprocessor has been obtained by EE Times. The floor plan of the chip indicates a massive floating-point unit. This would be in keeping with Intel's stated design goal of keeping Merced's performance in step with anything its RISC competitors can throw at it. However, an initial inspection of the floor plan appears to show that, rather than loading the chip down with dozens of execution units in a bid to enable numerous instructions to run at the same time, Intel's designers may have taken a more elegant approach toward parallel computing. Merced, due to ship in 2000, is the first processor to implement Intel's IA-64 architecture and its Explicitly Parallel Instruction Computing (Epic) technology. Epic has been billed as a new approach that applies some concepts from very-long-instruction-word (VLIW) computing but is altogether different. Essentially, Epic is intended to enable Merced to handle a large number of instructions and feed them to multiple, on-chip functional units for execution on every clock cycle. Intel officials declined to comment on the floor plan. Hewing to a public policy of releasing "incremental information," Intel has provided infrequent updates on its progress toward getting Merced silicon ready in time for shipment. Indeed, recent industry scuttlebutt focused on whether Intel would make its deadline. However, during a recent public update at the Intel Developer's Forum, held in Palm Springs, Calif., Albert Yu, general manager of Intel's microprocessor products group, told the audience that development was on schedule. "I am happy to report to you we are on track to get our product in production by the middle of 2000," he said. "The logic is basically complete. We are doing exhaustive testing at this moment. The circuit design and layout are on track." That is evident from the Mer-ced floor plan obtained by EE Times. Along with the impressive floating-point unit (FPU), which occupies approximately 10 percent of the chip's real estate, Merced also has some very traditional functional blocks common to most microprocessors. These include a memory-management unit and memory-interface unit. There is also a small area devoted to "applica- tion-specific extensions (ASE)." It's unclear what these might be, though it's possible the block allows for different interface-related implementations of even extra PAL space for future instructions. Keeping time Perhaps the most interesting detail in terms of physical layout is the strategy Intel has chosen for Merced's clock. Distributing the clock throughout a massive microprocessor is a vexing issue for designers, because signals can take different amounts of time to reach far-flung parts of the chip. This clock skew can wreak havoc with efforts to keep the chip running in sync. Designers have attacked the challenge in different ways. For example, Digital's Alpha microprocessor features a large, tuning-fork-shaped clock-distribution bus that reaches through almost the entire length of this chip to minimize skew. However, unlike Digital, Intel's engineers appear to have decided to liberally sprinkle clock distribution points throughout Merced's floor plan. According to Intel sources, Merced will decode and execute existing 32-bit X86 instructions in hardware. This function might be handled by the floor plan block labeled "DXU." What's most glaringly apparent about the Merced floor plan is that much of the chip's operation can't be gleaned from a cursory inspection. A host of new acronyms appear on the floor plan. They aren't defined in any public Intel documentation and Intel won't comment on them at this time. Since the hallmark of Intel's VLIW-like Epic technology is the ability to execute numerous instructions simultaneously, the most interesting aspect of the floor plan is determining just where this will occur. Some signs appear to point to the logical instruction unit (LIU), which is the only functional block on Merced as large as the FPU. The LIU is located in the bottom middle of the chip, occupying approximately 10 percent of its die. Most of the other functional blocks appear intended to handle the supply of instructions and data to the LIU. In the register department, Merced has 128 registers, each 64 bits wide, which are accessible by the programmer. (Other registers are used internally.) There are also sixty-four 1-bit predicate registers. These are used in conjunction with predication and speculation, which are the dual bulwarks of the IA-64 architecture. Predication removes branches from code by essentially executing both pre- and post-branch instructions at the same time. Then, the results from instructions that wouldn't have been executed during a real-world sequential run through the code are thrown out. Speculation masks memory latency by essentially yanking load instructions out of their normal place in the middle of a branch, and brings them forward to be initiated as early as possible in the program flow. Finally, Merced includes a full complement of performance-monitoring registers. These include registers that keep a running count of, for example, instructions per second and cache misses. The registers can be monitored in real-time without hardware slowdown, without impacting the actual execution of the code. According to an Intel official, the Merced instruction set will be made public in early 2000. Intel's next scheduled update on Merced is set for mid-October at the 1998 Microprocessor Forum, in a talk titled "IA-64 Processors: Features and Futures."