Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Vitesse Semiconductor -- Ignore unavailable to you. Want to Upgrade?

To: The Ox who wrote (1821)	10/8/1998 9:00:00 PM
From: jef saunders	Read Replies (1) \| Respond to of 4710

i bought vtss a couple of years ago, for the long term. i've been getting quarterly statements, every one a record. now i tuned in and it's in the teens...geesh! has anything fundamentally changed? did they warn the last month or something? thanks, jeff

To: The Ox who wrote (1821)	10/8/1998 9:00:00 PM
From: Lionel Parker Perkins III	Respond to of 4710

Stock will be back above 25 by earnings announcement as long as there is no pre-announcement before then. Each day no news is good news!!!!!

To: The Ox who wrote (1821)	10/9/1998 12:21:00 AM
From: Beltropolis Boy	Respond to of 4710

Announcements such as this continue to validate VTSS's business plan. there's more where that came from, michael. read on ... LAN/WAN effort at Vitesse & TI Electronic Buyer's News October 05, 1998, Issue: 1129 Section: Communications Mark LaPedus and Darrell Dunn Two chip makers are taking different, competing approaches in an effort to reduce the overall costs of high-end LAN/WAN equipment aimed at 2.5-Gbit/s-bandwidth applications. Vitesse Semiconductor Corp. this week will announce two components built in its high-speed gallium arsenide (GaAs) process technology, while Texas Instruments Inc. is providing a CMOS-based ASIC approach to the problem. Other companies, including Applied Micro Circuits Corp. (AMCC), have recently announced 1- and 2.5-Gbit/s products based on traditional bipolar chip technology. Vitesse, based in Camarillo, Calif., will expand its family of 2.5-Gbit/s physical-layer ICs with the introduction of two discrete devices for SONET/SDH applications: the VSC8120, a clock and data recovery unit (CRU); and the VSC8121, a clock multiplication unit (CMU). Vitesse's new devices are targeted at high-end OC-48 (2.5-Gbit/s-bandwidth) applications, such as Dense Wavelength Division Multiplexing (DWDM) systems, digital cross-connect units, SONET connections, and terminal equipment, said Robert Nunn, vice president and general manager of Vitesse's Telecom Products Division. For these and other applications, GaAs remains the technology of choice, according to Nunn. "No one ever thought that GaAs would ever become affordable or stable enough [for mainstream applications]," he said. "We compete very effectively against bipolar technology." Built using the company's proprietary GaAs technology, dubbed H-GaAs, the VSC8120 and VSC8121 provide flexibility at low prices. The products can be sold separately or integrated with Vitesse's mux/demux devices. The VSC8120-which uses a selectable-input reference clock of either 19, 39, 78, or 155 MHz-sells for $90 in 1,000-piece lots, and comes in a 64-pin PQFP. The VSC8121, in a 44-pin PQFP, costs $50 in similar quantities. Both devices are now sampling, with production slated for the end of this year. TI, meanwhile, has taken another approach. The Dallas-based company is offering an ASIC that can integrate up to 32 separate 2.5-Gbit/s serial data links and custom logic using a serializer/deserializer (SERDES), which is implemented fully in 0.25-micron CMOS technology. The application of CMOS technology enables higher integration and reduced power consumption compared with GaAs and bipolar technology, according to Brett Butler, director of core networking products for TI's ASIC group. At 2.5 Gbits/s, the SERDES core typically consumes 200 mW, or 70% less than existing alternatives, Butler said. The salability of the core allows the creation of a switching network capable of 512 Gbits/s by integrating multiple SERDES cores in a crossbar architecture. The core supports full-duplex data transfers with integrated clock-generator and clock-recovery modules. At 0.25 micron, TI can implement up to 1 million gates of logic with the SERDES core. The company plans to move the technology to a 0.18-micron process by year's end, which would allow up to 4 million logic gates, Butler said. Pricing will depend on the implementation and number of gates used. Copyright ® 1998 CMP Media Inc.