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To: Paul Engel who wrote (66140)10/9/1998 2:43:00 PM
From: Scumbria  Respond to of 186894
 
My guess is that Intel's fab success with the HP PA-8500 and excellent yields prompted them to redesign the new core with a VERY LARGE L1 cache - 1 MegaByte or possibly LARGER ~ 2 MegaBytes

Paul,

Can you elaborate on this statement? Are you saying that Intel is building a single-cycle 1MB cache at 1 GHz? That would be quite remarkable and quite unbelievable using the current definition of an L1 cache.

Windows uses a 4K page size, which implies a 256 way cache at 1MB. I don't think it would be possible to do a 256 way tag compare and retrieve the data from a huge array in <1ns.

I suspect that they will either use a small single-cycle L0 cache combined with a large multi-cycle L1 cache, or have a single large pipelined multi-cycle L1 cache. Those options would fall within the realm of physical possibility.

Scumbria