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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Maxwell who wrote (39178)	10/13/1998 3:08:00 PM
From: Steve Porter	Read Replies (2) \| Respond to of 1573682

Maxwell, If you are going to have a latency of 2 in your L1 cache, I can't agree with the strategy.. (btw: this is precisely what I meant by slowing the processor down). Would it not be possible to have a 1 latency L1 (say 64K) and then a 2 or 3 latency (additional) L2 on chip of say 256K and then off chip L3 on a BSB? (I know this would consume a fair ammount of silicon, but that's not the point ;-) ). By increasing your L1 cache latency to 2, (an increase of 1 clock), that 1 clock cascades down through the rest of the memory subsystem. This seems to be the backwards way to go. Also, are you sure about the 3, 3, 3 break of execution units (they didn't mention that anywhere that I can see). Steve