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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (39187)	10/13/1998 3:09:00 PM
From: Maxwell	Read Replies (1) \| Respond to of 1573683

Tenchusatsu: <<The K7 could also start with a full-speed L2 cache, but then the cost would knock K7 out of the mainstream and into the more expensive (but higher-margin) server/workstation market.>> You are correct. It would be a mistake to incorporate a full-speed L2 cache. In my opinion the large L1 would compensate for the performance loss due to half speed L2. The integer and fpu are very powerful and what make it attractive for server/worksation market. If it is cheap to make (unlike Xeon which uses very expensive L2 SRAM) AMD can afford to charge at lower price. Maxwell

To: Tenchusatsu who wrote (39187)	10/13/1998 3:12:00 PM
From: Kevin K. Spurway	Respond to of 1573683

Re: "Like Intel and the P6, AMD may want to push the K7 to different market segments by tweaking its off-chip L2 cache." They'll probably do a simple version: 128k L1, no full or half speed L2, just 200 MHz bus L2. This setup would probably be great for the low end, especially if it were mechanically compatible with socket 370.

To: Tenchusatsu who wrote (39187)	10/13/1998 3:13:00 PM
From: Joe NYC	Respond to of 1573683

Tenchusatsu, But since the L1 cache is 128K and the front-side bus is 200 MHz, the off-chip L2 cache would need to be huge, like at least 1 MB, in order to make a noticeable difference in performance. I think faster front side bus mainly increases the bandwidth, and helps latency only slightly, by making access to main memory more granular. (I could be wrong on this) Joe

To: Tenchusatsu who wrote (39187)	10/13/1998 4:26:00 PM
From: Profits	Read Replies (1) \| Respond to of 1573683

Tenchusatsu, The K7 bus is a 100MHz Double Data Rate Bus which offers 200MHz performance. And the backside L2 cache will be either 512K or 1M. As far as positioning goes, here's how I believe they'll position themselves: K6-2/300/333/350/366/380 vs. CeleronA-300/333/366 K6-2/400 vs. Pentium II-450 K6-3/450/500 vs. Katmai K7-500/550 vs. Willamette The big "Roadmap" that Intel released that supposedly showed around 10 processors is a bit deceiving. Reality is that Celeron, CeleronA, Pentium II, and Xeon are all built using the same P6 core. The only major differences are the amount of cache and the ability to do multiprocessing. P6 core ends at 450MHz. The Katmai, Tanner, Coppermine, Cascades and Willamette are all based on the Katmai core. The only differences here are again cache size, process technology, and bus speeds. Where Intel starts to differentiate itself is with the Merced and McKinley which frankly are not due out until the mid to end of 2000. AMD's roadmap matches up very nicely against Intel's, with AMD taking a slight performance lead with the Sharptooth processor in Q199 and a major performance lead with the K7 processor in Q299. As far as the KNI instruction argument goes, KNI is not supported in Microsoft's DirectX 6.0 and does not provide any real performance advantages over AMD's 3D-NOW technology. So I think that AMD's marketshare momentum will carry over into 1999 and will carry from the retail market to the commercial business market/notebook market and then into the server/workstation market with the release of the K7 processor. Profits