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To: REH who wrote (8526)	10/14/1998 11:22:00 AM
From: REH	Read Replies (3) \| Respond to of 93625

Intel to build bridge to Merced By Andy Santoni InfoWorld Electric Posted at 12:21 PM PT, Mar 10, 1998 Aiming to ease the transition from 32 to 64-bit CPUs, Intel next year will introduce an IA-32 processor that will fit into the same slot as the IA-64 Merced, according to an industry analyst. Quoting sources, Linley Gwennap, publisher and editor in chief of Microprocessor Report, in Sunnyvale, Calif., said the processor, code-named Tanner, "is designed to bridge the gap between the company's high-end x86 products and Merced." "Tanner, due to ship in 1999, is said to incorporate an x86 processor core, probably Katmai, along with an interface to the so-called Slot M interface that will be used by Merced," Gwennap explained. The processor would let users buy IA-32 systems that are "Merced ready," Gwennap noted. They could also buy systems with the same motherboards and system designs, with high-end workstations or servers based on Merced and midrange systems using Tanner, he noted. Gwennap expects Tanner to offer better performance than systems using Slot 2, the IA-32 interface for multiprocessor systems. "We expect Slot M to include a 128-bit bus, twice the width of Slot 2's bus. Slot M is also likely to run at 200 MHz, providing a peak bandwidth of 3.2 GBps, enough to match the bandwidth of a two-channel Direct Rambus DRAM memory system." Intel expects the transition from 100-MHz synchronous DRAM to Direct RDRAM to happen next year. Gwennap also expects Slot 2 to double in speed to 200 MHz next year, but that would only result in a peak bandwidth of 1.6 GBps. "While this performance is likely to satisfy the needs of most systems in that timeframe, high-end workstations and multiprocessor servers can make good use of the greater bandwidth of Slot M," Gwennap said. if this has been posted earlier I appologize