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To: Tony Viola who wrote (66738)	10/15/1998 1:47:00 PM
From: Paul Engel	Respond to of 186894

Tony 7 Intel Investors - Still More Details on Merced Note that the <erced will execute 4 EXTENDED PRECISION Floating Point operations in PARALLEL - or 8 SIngle precision FPOs in parallel. That confirms that the Merced will have 4 parallel FPU Execution pipes. This may go over big in Workstation Applications. Paul {===========================} ebnews.com Microprocessor Forum: Intel discloses more of roadmap By Mark Hachman Electronic Buyers' News (10/15/98, 10:29:02 AM EDT) A week after Intel Corp. outlined its 64-bit roadmap through 2000, the chip giant published a second edition. As part of a presentation at this week's Microprocessor Forum, Stephen L. Smith, corporate vice-president of Intel's Microprocessor Group, added the names “Madison” and “Deerfield” to its 64-bit roadmap. At the same time, he provided some additional details of the architecture of Intel's first 64-bit chip, Merced. Intel's previous 64-bit roadmap ended in 2002, where Merced's successor, McKinley, was scheduled to give way to a pair of unnamed derivative chips. Madison, a processor created for high-performance applications, will be the first of these previously unnamed products. Deerfield, by contrast, will try to strike a balance between performance and relatively low cost. Smith said that Merced's 3D graphics performance would be 20 times the Pentium Pro, but 3 times the performance of 1999's 32-bit Tanner chip. Merced's performance will hinge upon four main areas, Smith said: a combination of single- and multiple-precision floating point units; dynamic execution of 32-bit code; plus a three level cache hierarchy. In addition, Merced's Error Correction Code (ECC) will prevent errors on the Level 1 cache, Level 2 bus, Level 2 cache, and front-side system bus. Essentially, the floating point architecture will allow either 8 single-precision floating point operations or 4 “extended-precision” floating point operations in a single cycle, Smith said. Through a control bit, Merced will be able to distinguish between a 32- and 64-bit instruction. “Essentially, a 32-bit instruction is issued as 64-bit (operation) code,” he said. Finally a level 0, 1, and 2 cache will help speed performance. But analysts were struck by the similarity between Intel's 32-bit and 64-bit performance estimates, especially concerning the comparisons of 3D graphics performance. Last week, Fred Pollack, an Intel fellow and director of the Microprocessor Group's measurement, architecture and planning (MAP) business, said that OEMs will choose between a 32-bit and 64-bit processor based upon the software code written or compiled in each format. “There's a lot of problems right now for Intel,” said Linley Gwennap, vice-president and editorial director of MicroDesign Resources' MPU report, Sunnyvale, Calif. “More specifically, the performance that Merced will have -- which was originally expected in 1999, now in 2000 -- is not significantly ahead of the IA-32 architecture.” Last week, Intel executives predicted OEMs would design systems using 32 Merced processors running in parallel. But Smith said today that OEMs will design multiprocessing systems using up to 256 Merced chips.

To: Tony Viola who wrote (66738)	10/15/1998 2:13:00 PM
From: Len Roselli	Read Replies (1) \| Respond to of 186894

Tony, Thanks for your insider's information on IBM's process technology. This is the text of the AD I referred to: "ICE announces publication of the first detailed physical (construction) analysis on the first IC product t use COPPER interconnect. "THe report (#SCA 9808-587) covers the IBM Power PC750 microprocessor that is implemented with 6 levels of damascene defined copper interconnect. In addition, it incorporates 0.12 micron gates!" "This is easily the most advanced process in the industry and clearly illustrates IBM's technology prowess." len