Intel Details Road Map Through 2000
Oct 08, 1998 (Tech Web - CMP via COMTEX) -- Responding to recent
product road maps published by other RISC microprocessor vendors, Intel
disclosed more details about new 32-bit and 64-bit microprocessors as a
prelude to the its 1-GHz milestone.
Typically, Intel executives have chosen to brief OEMs privately,
disclosing product revisions and new technologies in front of a
selected panel of hardware and software vendors. Wednesday, however,
company executives provided those same details to reporters in a bid to
tap into a larger customer base, including new workstation and server
customers.
Intel executives concentrated on two processors due around the turn of
the century: Foster, a newly disclosed 32-bit microprocessor; as well
as McKinley, the successor to Intel's first 64-bit chip, Merced. All
three chips are designed for workstations and servers only.
"The Intel architecture has taken a significant role in the workstation
and server market," said Fred Pollack, Intel fellow and director of
measurement, architecture, and planning for Intel's Microprocessor
Products Group, in Santa Clara, Calif. "Customers expect you to roll
out a much longer road map. To be a very serious player -- it was
something we needed to do. Our segmentation strategy is designed to
take the Intel architecture from the lowest-end desktop to the
highest-end server."
In 32-bit high-end processors, Intel's road map now extends from next
year's Tanner chip through Cascades, a 0.18-micron processor with
integrated Level 2 cache. From there, OEMs may choose to purchase a
64-bit Merced chip in early 1999, or turn to Intel's next 32-bit
offering, Foster, in 2000 or 2001. Foster chips are designed for
systems costing about $3,000 to $9,000.
At that time, Intel's server and workstation offerings will begin with
Willamette, a desktop PC processor doing double duty as a high-end
chip. Willamette-based servers and workstations will be priced just
under Foster-based systems, much like the Pentium II is used in
conjunction with Intel's Xeon processors. Willamette chips will be
included in under-$3,000 workstations. Even higher-end software such as
EDA tools will require a Merced chip, Pollack said.
OEMs wondering which processors to purchase will be forced to judge the
availability of software for each type of architecture. For example,
Foster and Merced are actually about equal in calculating floating
operations used for multimedia, and even Merced's successor, McKinley,
will be slower than Foster in calculating 32-bit integer calculations,
Pollack said.
But that 32-bit software can and will be recompiled to harness the
speed of Intel's 64-bit chips, where Foster can't keep up. That will
help speed the industry's conversion away from 32-bit microprocessors,
Pollack said.
Intel will also help the 32- to 64-bit transition by designing
different versions of one eight-way chip set, designed for both the
32-bit Foster and 64-bit McKinley chips, roughly about 2001. As EBN
previously reported, a similar transitional chip set was designed for
the Tanner processor, but was shelved when Merced's introduction was
delayed.
Much like the Pentium Pro and Pentium II marked the next generation of
Intel's chips, so will Foster represent a new 32-bit design, Pollack
said. While features such as dynamic execution and superpipelining will
help the chip execute instructions faster, Intel will add a feature
called a "trace cache" of an undisclosed size. Essentially, this trace
cache will eliminate the need to decompress the instructions
themselves, eliminating a step in the processing procedure.
Foster's system bus to main memory will run at a blazing 3.2 gigabytes
per second, compared with the 800-megabyte bandwidth allowed by Intel's
current processors. That will allow two channels of Direct Rambus
memory, Pollack said. Foster can be used in two-way or four-way servers
using the Colusa chip set, he said.
Willamette, Foster, Merced, and all succeeding microprocessors will
integrate L2 cache directly onto the die. Intel's processors will not
use discrete SRAM chips as Level 3 cache, Pollack said, adding fuel to
analysts' belief that the cache SRAM market may be nearing the end of
its life.
Analyst company In-Stat, in Scottsdale, Ariz., said it estimates this
trend will cause the discrete SRAM market to shrink from $4.18 billion
this year to just $2 billion in 2002.
"A lot of OEMs are designing their own [64-bit]chip sets. Our customers
really wanted to differentiate themselves." -- Fred Pollack Intel To
date, industry attention has focused upon Merced, Intel's first entry
into 64-bit computing. Pollack said Merced's sample date remains
unchanged, scheduled for early 1999. According to Pollack, the
microarchitecture, or deciding what functions the chip will perform,
has been completed for a long time.
Now, Intel's engineers are concentrating upon the layout of Merced's
functional blocks even as they begin testing 64-bit operating system
software on a simulated Merced design. Intel will also open up to 25
centers worldwide to let software vendors test their work on
Merced-based systems.
Merced-based workstations and servers will largely be architected by
Intel's customers themselves. "A lot of OEMs are designing their own
[64-bit]chip sets. Our customers really wanted to differentiate
themselves," Pollack said.
Thus, Intel's customers will design chip sets to allow up to 32 Merced
chips to run in parallel. To get them rolling, however, Pollack said
Intel will design multiple versions of chip sets supporting up to only
four microprocessors, Those chip sets will interface to both cheap
SDRAM and the more expensive, higher-performance Direct Rambus DRAM
Intel has endorsed.
At the end of 2001, Merced will become gradually replaced by McKinley,
Intel's first 1-GHz chip that will also be produced on Intel's 0.18
silicon process that uses copper interconnects.
Pollack called McKinley "somewhere inbetween" a Merced clone and a
redesigned chip. "There were things learned in the design with Merced
that we didn't like to do, that we would have liked to go back and do
again," he said. "Of course, we can't do that."
In McKinley, Intel increased the number of units that execute the
processor's instructions, while shortening the "pipeline," or path, in
which those instructions process the data.
Together with the largest amount of integrated cache memory of any
Intel microprocessor, Pollack said he expects Merced to produce twice
the performance of the Merced chip. At least two derivatives of
McKinley are expected, emphasizing either performance or low cost.
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