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To: George W Daly, Jr. who wrote (66779)	10/15/1998 6:45:00 PM
From: Glenn D. Rudolph	Read Replies (1) \| Respond to of 186894

INTC: BANCBOSTON RS decreased estimate for quarter ending 12/99 from $1.15 to $1.13 on 10/14/98 INTC: BANCBOSTON RS increased estimate for fiscal year ending 12/98 from $3.20 to $3.35 on 10/14/98 INTC: BANCBOSTON RS increased estimate for quarter ending 03/99 from $0.93 to $0.95 on 10/14/98 INTC: BANCBOSTON RS increased estimate for quarter ending 12/98 from $0.89 to $0.94 on 10/14/98 INTC: BEAR STEARNS increased estimate for fiscal year ending 12/98 from $3.15 to $3.30 on 10/14/98 INTC: BEAR STEARNS increased estimate for fiscal year ending 12/99 from $3.75 to $4.00 on 10/14/98 INTC: BEAR STEARNS increased estimate for quarter ending 03/99 from $0.91 to $0.98 on 10/14/98 INTC: BEAR STEARNS increased estimate for quarter ending 06/99 from $0.91 to $0.98 on 10/14/98 INTC: BEAR STEARNS increased estimate for quarter ending 09/99 from $0.94 to $1.00 on 10/14/98 INTC: BEAR STEARNS increased estimate for quarter ending 12/98 from $0.87 to $0.94 on 10/14/98 INTC: BEAR STEARNS increased estimate for quarter ending 12/99 from $0.99 to $1.04 on 10/14/98 INTC: FAHNESTOCK increased estimate for fiscal year ending 12/98 from $2.95 to $3.04 on 09/30/98 INTC: FAHNESTOCK increased estimate for fiscal year ending 12/99 from $3.45 to $3.54 on 09/30/98 INTC: Major Broker increased estimate for fiscal year ending 12/98 from $3.05 to $3.18 on 10/14/98 INTC: Major Broker increased estimate for fiscal year ending 12/99 from $3.70 to $3.85 on 10/14/98 INTC: Major Broker increased estimate for quarter ending 03/99 from $0.87 to $0.91 on 10/14/98 INTC: Major Broker increased estimate for quarter ending 06/99 from $0.89 to $0.93 on 10/14/98 INTC: Major Broker increased estimate for quarter ending 09/99 from $0.93 to $0.97 on 10/14/98 INTC: Major Broker increased estimate for quarter ending 12/98 from $0.88 to $0.92 on 10/14/98 INTC: Major Broker increased estimate for quarter ending 12/99 from $1.01 to $1.04 on 10/14/98 INTC: NATNBK MONT.SEC increased estimate for fiscal year ending 12/98 from $3.17 to $3.19 on 10/14/98 INTC: SUTRO & CO has reiterated estimate for long term EPS growth of 17.00% per year on 10/14/98 INTC: SUTRO & CO increased estimate for fiscal year ending 12/98 from $3.15 to $3.27 on 10/14/98 INTC: SUTRO & CO increased estimate for fiscal year ending 12/99 from $3.75 to $3.83 on 10/14/98 INTC: SUTRO & CO increased estimate for quarter ending 12/98 from $0.81 to $0.92 on 10/14/98

To: George W Daly, Jr. who wrote (66779)	10/15/1998 8:49:00 PM
From: Mary Cluney	Read Replies (1) \| Respond to of 186894

George, >>>Semi-conductors at IBM started LONG before Mr. Gerstner arrived. This kid knows how to pitch and is demonstrating it. <<< I'm sorry to sound so ridiculus to you, but all I was trying to do was get a handle (mostly for my own sake) as to "who is ahead" in semiconductor development. I do know that IBM has been around a lot longer than Intel and that IBM is still very competitive in semiconductor technology - and I'm sort of aware of their efforts at Lawrence Livermore with their supercomputer activities. I am also aware that Lou Gerstner has been quite successful at IBM - in bringing them back to profitability and in increasing shareholder value. But, going forward - especially in the semiconductor part of the business - I would think that Craig Barrett knows far more of the nuts and bolts of semiconductor technology and can provide a more focused vision as to where the company and the industry is headed vis-a-vis semiconductors than Gerstner can. Gerstner, himself, has admitted he does not have a vision for IBM. And, I can't imagine where he could have a vision for the semicodnuctor part of the business. I know, I know - you're going to tell me he doesn't need to know anything about it - all he has to do is appoint the right people to the jobs. If that is what you are going to say - that is where I would disagree. Whenever the Boss doesn't know the subject and has to rely on people (as George Steinbrenner would say - my baseball people - sorry, tony) - there are always going to be factions trying to gain his support - and what you get is that proverbial camel when the designers were trying to design a horse. I hope I don't sound too ridiculous. Regards, Mary

To: George W Daly, Jr. who wrote (66779)	10/16/1998 1:16:00 AM
From: Tony Viola	Read Replies (1) \| Respond to of 186894

George, Re: "I expected more from Tony and Paul, who know better, than to equate process line capability to chip MHz. Its a function of how much logic you want to accomplish in a cycle." OK, you're right there. It is the MIPs, FLOPs, SPECints or SYSmarks that really count in benchmarking and comparing processors. They measure the work that gets done. However, in the microprocessor world, MHz has become king and most quoted parameter by far. It's sort of assumed that all the various processors will get the right amount of stuff accomplished in each CPU cycle. I mean, this is obvious stuff, that Megahertz is it now, rightly so, or not. What other parameter do all the x86, SPARC, MIPS and Alpha vendors quote first? System 390 is the only well known (is it still?) machine that quotes a throughput parameter, MIPs, first. Cycle time, or clock frequency is right behind it, though. Well, in any case, George, stick around. This (and other) threads can help us keep on our toes, and that can't hurt (usually?). Tony

To: George W Daly, Jr. who wrote (66779)	10/16/1998 2:13:00 AM
From: Paul Engel	Read Replies (1) \| Respond to of 186894

George - Re: " I expected more from Tony and Paul, who know better, than to equate process line capability to chip MHz. Its a function of how much logic you want to accomplish in a cycle " You are clearly confused. Process line capability - that is gate length, is a first order determinant of process speed, or MHz. Re: "how much logic you want to accomplish in a cycle" The amount of LOGIC performed in a clock cycle is dependent entirely upon circuit design and logic architecture. A simple transistor will toggle at a frequency dependent upon gate length as well as many other process parameters but will accomplish essentially NO LOGIC FUNCTION by itself. LOGIC Per CYCLE and CYCLES per Second (MHz) are two SEPARATE but interelated issues - poor logic design/circuit design will slow down CYCLES per second. Paul