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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: MileHigh who wrote (39441)	10/15/1998 9:28:00 PM
From: dumbmoney	Respond to of 1573505

I hear much about the latency issue surrounding RDRAM. Can the architecture or design layout be improved to take care of this issue? Or is this not possible? Older Rambus designs had big problems with latency, but DRDRAM is okay. The basic latency is the same as standard 100Mhz SDRAM. Further, DRDRAM does a great job with random-access bursts.

To: MileHigh who wrote (39441)	10/15/1998 9:41:00 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 1573505

MileHigh, re: <I hear much about the latency issue surrounding RDRAM. Can the architecture or design layout be improved to take care of this issue? Or is this not possible?> Bret McComas, in his articles posted on www.tomshardware.com, mentioned ESDRAM, or low-latency SDRAM, as an alternative to RDRAM. I'm not very sure how ESDRAM achieves the lower latencies that Bret describes. But in an e-mail exchange w/ Bret, he mentioned to me that ESDRAM could be about twice the cost of SDRAM, compared with RDRAM's 30% price premium over SDRAM. Also, ESDRAM may not be able to go much faster than 133 MHz, while RDRAM already promises a bandwidth equivalent to a 200 MHz SDRAM DIMM. But I'll bet you're still wondering why latency is a factor in the first place. Well, latency is just a side effect of modern DRAM's, where every bit in memory is represented by a capacitor and a transistor on the silicon. This form of memory allows for high memory densities at very low costs, but because of the capacitor, the penalty is speed, hence the latency. We can easily reduce latency by switching from DRAM to SRAM, where every bit in memory is represented by four transistors. Of course, SRAM is crazy expensive compared to DRAM, and you can't pack as many bits into a given area of SRAM silicon as you can into a given area of DRAM silicon. That's why you have the cache hierarchies that you see today. L1, L2, L3, even L0 in the case of Merced. Tenchusatsu