Test industry's annual bash opens amid 'worst downturn' ever -- ATE sees system-on-chip as a way out of rut
techweb.com
Stan Runyon
>>Washington - The International Test Conference (ITC) opens here this week amid economic turmoil in the semiconductor and ATE industries. But the test industry's salvation may be system-on-chip (SOC) testing.
Bloated capacity in memory-chip fabrication, plunging PC prices and the spreading Asian economic crisis have teamed up to set off one of the worst downturns in a long time. The market for memory ATE equipment may have plummeted to half of what it was last year, said Tom Newman, vice president at test maker Teradyne Inc. And sales of mixed-signal and logic testers could be off by 30 percent, according to projections by VLSI Research Inc.
Ordinarily, such a slump would be viewed as just another cycle in a series of periodic disruptions that have beset the two industries for almost three decades: the semiconductor industry sneezes and the ATE industry catches a cold. But in this case, the unexpectedly steep plunge may lead to a somewhat graver diagnosis.
"This has been the worst downturn any of us have seen, although the U.S. and Europe still are bright spots," said Keith Barnes, the chief executive officer at Integrated Measurement Systems, a specialist in engineering and debugging ATE systems.
Speaking at the NationsBanc Montgomery Securities conference last month in San Francisco, Jerry Fishman, chief executive officer of Analog Devices Inc., a big supplier of pin-electronics driver chips for test systems, noted that the depressed state of the ATE industry was eating into his company's sales at the staggering rate of $25 million a quarter. "When the demand in the test business recovers, we see it first and so far, we haven't seen it," Fishman said.
Joseph Bronson, chief financial officer at Applied Materials Inc., the largest vendor of semiconductor equipment, warned that chip demand might never return to its historical growth rate.
And Neil Kelly, chief technologist at LTX Corp., said, "This is more than just a cyclical downturn. There is a fundamental change going on which will result in a different driver for the semiconductor industry. Semiconductors no longer will be differentiated by process technology, but by intellectual property."
But, said Dan Hutcheson, president of VLSI Research, some of that pessimism is "a good sign. When everybody is convinced it's never going to turn around, that it's no longer cyclical, a mature industry, that's when it will turn up with a bang."
The biggest obstacle to a turnaround, said Hutcheson, is the expectation of a sharp turnaround. "That keeps people holding on to their infrastructures and present capacities. They ignore their fixed costs and shift to variable costs, losing money in the process."
As a result, Hutcheson expects the equipment market to be off about 30 percent this year. "Next year we'll be lucky if it's flat, partially because the industry has discounted its equipment by about 30 percent. That says we're still shipping as much capacity as a year ago."
Still, Hutcheson pointed out that "ATE is not as bad off as assembly. But some areas are bloody, like memory test. A big hang-up is that DRAM vendors don't want to pay the royalties for Rambus, so they're pushing their synchronous DRAMs as hard as they can. Because of that, they don't need new memory testers."
The conclusion: There is buying, but to meet emerging technology, not to increase capacity. In the first quarter of 1997, the industry possessed about 150 fabs' worth of wafer capacity-35 million wafers a year. In the middle of 1998, there are about 175, with a capacity of 42 million wafers. Meanwhile, die shrinks and higher yields are producing even more chips from each wafer.
"People are very nervous about that," said Tom Newsom, vice president of sales, marketing and support at Hewlett-Packard Co.'s Automated Test Group.
"They are investing only after they try to make do with what they've got or hit a technology wall: speed, complexity, embedded memory, new mixed-signal devices and new package types, such as ball-grid arrays or chip-scale packages," Newsom said.
"Making do" means shrinking die sizes, and the ability to do that has hit front-end equipment more than back-end ATE. Historically, adding capacity by shrinking dice results in a loss in yield, which requires a capital-equipment expenditure to compensate. Today, with new fabrication techniques, yield can be improved as chips shrink. The upshot: Less money is spent on etching and lithography tools.
However, the back end feeds on pin or transistor count. Both of those are rising and that means checks must be written for ATE systems, Asian flu or not.
In any case, Hutcheson, for one, believes the recession is not related to the Asian financial crisis. "The real problem is that the PC [sales have] slowed. A lot of the blame goes to Microsoft-it has done everything it can to hold off technology," he said. "No one needs a 450-MHz machine for Windows 98 and Office 97."
Winners and losers
Whatever the cause, the effects of the ATE dropoff, aside from memory test, are distributed unevenly. LTX is noticeably absent from ITC this year, although it was one of the first to address SOC testing with its Fusion ATE system. Unfortunately, Fusion-even with its capability for testing almost anything on a chip-may be a bit early.
"The Fusion is a beautiful machine and it looks like it will do great," observed Jerry Hutcheson, chief executive officer of VLSI Research, "but the market's not quite ready for it. Meanwhile, the rest of LTX's market is dropping off, so they're going through some hard times."
Credence Systems, which does a lively business with test and assembly contractors, also may be suffering a bit more than others.
"The biggest difference this time," said Bill Bottoms, chief executive officer, "is the steepness of the decline. After being up 72 percent year-over-year in our second fiscal quarter, we plunged by half in our third quarter. We were not expecting that."
Who will thrive? "Advantest, Teradyne and Hewlett-Packard are the ones with the real strength," said Jerry Hutcheson. "They've moved out and forward."
Teradyne Inc., for one, appears to have less exposure than most in the high-risk regions: Korea, Japan and Taiwan. According to Tom Newman, a vice president, just 33 percent of the company's $1.27 billion in 1997 revenues came from Asia.
Although the ATE industry appears to be down across the board, analog and mixed signal appear to have held up the best. That and diversification may keep the economic dike from being breached altogether and secure a better future for the industry, at least in the long run.
For instance, Teradyne is involved in testing for interconnects (chips and boards), software, automatic inspection and other areas. Credence and HP have branched out, too. Schlumberger has broken the barrier to flip-chip testing with a non-contact laser-beam approach. Advantest has been pushing hard in logic and is preparing for the gigahertz age.
All the major players have responded to user demand and have developed a broad range of price points. Witness Teradyne's J750 Integra, a low-to-midrange 100-MHz, 1,024-pin VLSI tester launched last spring. The company is showing a memory-test option at ITC.
Many of the new contenders are tackling the Rambus and superchip test problems, with a variety of imaginative solutions. But is that enough to pull the industry back?
Maybe, but to some industry observers this is not an ordinary downturn. Something fundamental has changed, they say.
The switch to logic
Supporting that argument is the chip makers' rush to switch from fabricating semiconductor memories to logic, a feat that is easier to achieve on paper than in the factory. Almost every major memory-chip vendor is trying to change the mix, to get away from predatory, disastrous pricing in standalone memories and avoid getting caught as designers integrate more and more memory on-chip. The reviews are still coming in on whether the switch has been successful.
"The hard part about switching to logic," explained Dan Hutcheson, "is that so much is tied up in the test programming, it's difficult to switch vendors; people have to be trained. Then, there's the legacy of all the personality boards and other hardware that have to be managed during the transition."
Yet some chip makers are undaunted, pointing out that the surprise may be in Japan. "We think we're gaining share in logic test there," Teradyne's Newman revealed. "We've had amazing luck because customers are converting from DRAM to logic."
Teradyne's experience may partially explain why ATE is not reeling from the
downturn as much as the front-end supply chain. But others describe a
different experience.
"This one is different because almost all the major Japanese players, with the
exception of NEC and Fujitsu, have abandoned manufacturing in the U.S.,"
said Phil Philips, vice president of sales for Advantest America. "They didn't
invest in new devices and tried unsuccessfully to switch to logic."
One bright spot for the future of ATE, according to Philips: emerging Rambus
memories. "It will help the equipment companies," he stated, "but not
necessarily the chip vendors in terms of price stability."
Some believe that little has changed, that equipment sales actually have
reached their low and are about to turn up. "Business has picked up in
Taiwan, much to their surprise," Tom Newsom said, "but they don't know if
it's a long-term trend."
"It's just another down cycle for ATE," said Credence's Bottoms, "just more
violent because of the pressures on our customers."
According to Integrated Measurement's Barnes, the ATE industry will begin
to benefit from increased volume toward the end of 1999 or early 2000 and
recovery will take place in four stages. For the first stage, "watch the EDA
companies," he advised. "They're working on a lot of new designs."
For that matter, Integrated Measurement itself bears watching: Its shipment of machines relates to activity in prototyping new designs, which should show up in production later on. Indeed, at ITC, the company is rolling out Vanguard, a 500-MHz digital tester; Electra, a new mixed-signal platform, and Orion, a system that takes Integrated Measurement into memory testing for the first time.
Another good sign: Most of the major ATE houses are bringing new iron to ITC, including Credence (Duo, for mixed signal, digital and memory, and Quartet, sporting RF to 6 GHz and some new features) and HP (wafer probing to 18 GHz, integrated high-speed test work cells, and a 1,024-pin, small-footprint system).
For its part, Schlumberger ATE is rolling out and shipping four new machines over the next quarter, including testing solutions for thermal control, Rambus chips, flip chips and SOCs. "There is light at the end of the tunnel but we're struggling like everyone else," said Carlos Lazalde, president of test and transactions, Semiconductor Group/North America.
Testing superchips
What is unarguably different about this downturn is the semiconductor industry's breathtaking departure from Moore's Law: It is leaping into an age of almost unbelievably dense, superfast chips.
But call them superchips, SOCs or core-based ICs, the problem is the same:The testing demands of advanced ICs are mounting to a technological
crescendo just as the economic health of the ATE industry is heading the other
way.
Given the huge investments necessary to produce ATE systems that can rise
to the challenge economically-and with the nature and onset of recovery
uncertain-the stage is being set for a reshaped ATE community within the next
few years.
In the near future, superchips will carry all or most of a system's functionality,
including the analog, digital and memory portions. Even front-end RF and
microwave circuits are beginning to integrate with logic on a single chip.
System memory, embedded deeply or even within another core, will vary in
variety and capacity. And these are not merely token memories: Capacities of
32 and 64 kbytes are not unreasonable in the near future. Already, some chips
have been produced that sport over 100 different kinds of memories and
perhaps closer to 200.
The business picture may be uncertain but the ATE manufacturers believe that
they see the technological future with better clarity. "The semi-equipment
recession has amplified the shift to newer, more in-tegrated technologies," said
Roger Blethen, president of the LTX Corp., "especially in the area of test."
"There's little growth left in the purely digital ATE market," Credence's
Bottoms concurred. "We're facing products that hold high-performance logic,
audio, video and RF on the same piece of silicon. Communications will be a
stronger driver than PCs."
That may be true, but it's hard to tell from looking at a machine like
Teradyne's J973 VLSI tester. Aimed at complex chips and high-performance
microprocessors, such as AMD's K6, the J973 also offers scan testing and an
embedded memory test option, two attributes that will be part of the test
stable of SOCs.
The ATE industry must move now to establish a position in the future and to
factor in not only the move to blazingly fast Rambus memories and gigahertz
processors, but the severe pin and gate counts, I/O speeds and accuracies
projected by the SIA road map.
In fact, the Semiconductor Industry Association has expressed concern that
overall test accuracies of ATE, which directly affect yield, will not be able to
keep up with the requirements of advanced chips. The margin of error could
be astonishing-as high as 50 percent by 2012, if nothing is done.
It is likely that semiconductor vendors soon will demand timing resolutions and
accuracies in the low-picosecond region, perhaps 10 times better than those
of today's top testers.
For today, however, 25 to 50 ps or so is achievable and the ATE community
is exploring ways to shave that number even more. Schlumberger, for
example, is showing a system at ITC that bumps up accuracy 25 percent over
its earlier IX.
"The next-generation timing generators will need to double in speed and be at
least twice as accurate," said Allan Armstrong, ATE product marketing
manager for Vitesse. "We're talking up to three times as much chip
complexity."
ATE vendors are working on the timing problem. "The temporary downturn
has not affected the strong ongoing development effort we see in most of our
customers," said Vitesse's Gardener. "High-performance systems are driven
more by technology development than by up-and-down cycles. Our
shipments actually are ramping up."
"There's been a performance acceleration in test systems within the last three
years because of the test needs of processors and memories," Gardener
stated. "For the former, you'll see 2-GHz test capabilities by the year 2000.
Memory acceleration has been even faster: Rambus is up to 800 MHz."
Teradyne's Newman agrees. "We were surprised at the pace of progress in
chips," he admitted, "especially the degree to which a variety of capabilities
now are needed in a tester. For example, 100 percent of our logic testers now
go out with embedded-memory test capabilities, not the 50 or 60 percent we
had anticipated."
But Newman also is astonished at the amount of analog capabilities needed in
logic testers and digital capabilities in mixed-signal testers.
That others have felt that too is aptly demonstrated by "big iron" machines like
LTX's Fusion, HP's 83000, Schlumberger's IT 9000, Ad-vantest's 1-GHz
T6682 and Teradyne's Catalyst, most of which are competing for attention at
ITC.
Advantest also is sneaking in the T6682's compatible little brother, code
named SL1. Together, the two span zero to 1 GHz for SOC testing,
according to product manager Rick Crucsiel.
As Crucsiel explained it, SOC or system-level LSI testing demands three
components: mixed signal, embedded DRAM to 16 Mbytes and high-speed
interfaces. Of those, the new high-speed interfaces may pose the greatest test
challenge. After all, ATE systems have never encountered 800-Mbit/second
data rates before. Crucsiel's solution: Test some things at wafer probe, others
at final test.
In the battle over SOC dominance, Teradyne's Catalyst seems to have drawn
blood: More than 100 have been shipped since its debut only about a year
ago. "We're bringing the Catalyst 400 to ITC," said product manager Jeff
Schneider, "a step up in digital performance, with faster I/O and deeper
memory."
According to the product manager for Teradyne's Wireless Group, Gordon
Eddy, microwaves are Catalyst's next horizon and ITC will see the debut of
the Microwave 6000, with complete VNA (vector network analyzer)
capability to 6 GHz. And Bruce Webster, Teradyne VX simulation manager,
revealed the rollout at ITC of digital VX, VHDL/Verilog-based software for
presilicon debugging.
If anything, Catalyst appears to be a weather vane indicating which way the
economic winds are realigning the revenue-stream mix: mixed signal, followed
by logic, followed by memory. However, the appearance of test systems
capable of tackling Rambus memories in production-not just low-volume,
engineering-oriented systems-could change that mix.<<
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