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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: dumbmoney who wrote (67030)	10/19/1998 9:54:00 PM
From: Jules V	Respond to of 186894

Battle Lines Drawn For Next-Generation MPUs techweb.com Lots of material on the processors here. About K7: a contender according to AMD. Has hazards: The design lets AMD tout its very high performance, especially at target clock rates of more than 500 MHz. But it also exposes the company to a profound risk: Both the media instructions and the system bus will be incompatible with Intel's product line. AMD says: While Katmai remains a relatively stock Pentium II design with an extended SIMD unit, the K7 is a ground-up re-architecting of the IA-32 instruction set. With three general-execution units and three address-calculation units, K7 will be a wider superscalar machine than the Pentium II, said AMD's director of K7 engineering, Dirk Meyer. On the floating-point side, particularly for X87 code, the difference between the K7 and the Pentium II is even more apparent, he said. The K7 has two double-precision, fully pipelined X87 data paths, compared with one for the Pentium II -- which, according to Meyer, is not fully pipelined for double precision. "If you want to do an X87 instruction on the Pentium II, in one sense, you cycle the instruction through the pipe twice. So in some ways, for double-precision X87, the K7 has four times the peak execution rate," Meyer said. Because the 3DNow multimedia instructions are SIMD, in every register, there are two single-precision numbers, and two pipelines can operate on that data. So, essentially, the K7 provides twice the performance available on the Pentium II for X87 code, Meyer said. That more aggressive superscalar design is more demanding on bus bandwidth and decode/dispatch logic. AMD's answer is a 200-MHz system bus. Licensed from Digital Equipment, the EV6 bus is the same as that used for the Alpha 21264 processor, now owned by Compaq. The K7 will be placed on a daughtercard that is mechanically compatible with, though electrically different from, the Intel Slot 1 design, and Compaq could offer the Alpha on daughtercards to the commercial market, ensuring swappability with the K7 for system OEMs. If the EV6 bus can supply K7's caches with enough data, the bandwidth problem will pass on to the processor's decode and dispatch logic. Here, AMD has taken two major steps. First, IA-32 instructions are decomposed not into rudimentary RISC operations but into what Meyer called macro-ops -- slightly more complex steps that can include two rudimentary operations. The macro-ops are then heavily buffered throughout the decode, reservation and dispatch process to avoid stalls. "One thing that differentiates the K7 from essentially any other X86 processor is the deep buffers we have in place ... deep, deep instruction and memory schedulers and lots of memory and address data buffering," Meyer said. "The more bandwidth you have, the more buffering you need to sustain the bandwidth. We went to fairly great lengths to make sure the machine would have the buffering it needed to uncover all the work that is available in auto-decode."