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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Brian Hutcheson who wrote (39655)	10/20/1998 3:55:00 AM
From: Tenchusatsu	Read Replies (2) \| Respond to of 1578755

<The FPU of the PII as everyone in the PC press acknowledges is better than the K6 but the integer unit is slower , one reason is that K6 is a 6 issue execution unit as opposed to PII's 5 issue .> Big deal, since K6 couldn't use all those execution units efficiently. Every CPU benchmark shows that the P6 is superior to the K6 in integer instructions, especially those which are cache-independent. Also Microprocessor Report had an article showing the various design decisions and trade-offs between P6, K6, and other processors. For most code fragments, P6 executed more instructions per cycle than K6. I can post some details of that article if you want. Makes me wonder how well the K7 is going to keep all its pipelines filled. Adding more execution units, decoders, etc. isn't going to mean much if you can't uncover more instruction-level parallelism. There are more advanced ways to speed up the x86 architecture than SIMD or more pipelines. This doesn't mean that the K7 isn't going to be one powerful sucker, though. But it does make me wonder whether AMD is hitting the wall of diminished returns, knowing that the K6 wasn't as efficient as the P6 in integer execution. <The K6 also was designed with L1 cache twice the size of PII those 2 factors make the K6 core superior .> Are you also going to tell me that the Cyrix MII is superior to the K6 because its L1 cache is unified, which is obviously more powerful than an L1 cache divided into instructions and data? The MII and the K6 can get away with larger L1 caches because they aren't meant to be clocked as high as Pentium II. (Of course, getting the K6 core to 400 MHz is remarkable in itself, but those volumes are going to be miniscule compared to Intel's volumes on their latest-n-greatest.) More importantly, the K6 practically needs a larger L1 cache because of its lack of backside L2 cache. <The Celeron 266mhz was slower than a K6-200 that is sufficient proof that most of the "high performance" of the PII comes from the L2 cache on the daughter board since that is the only real diffference ,> So are you also going to argue that the P6 core is worse than the P5 core simply by showing that the Celeron 266 MHz is slower than a Pentium MMX 233 MHz? You might be able to convince some "Dilbert" managers with that kind of argument, especially if you use Powerpoint slides, but you're not going to convince people who know a little better. Tenchusatsu