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To: Fred Fahmy who wrote (67221)10/23/1998 12:20:00 AM
From: kash johal  Read Replies (2) | Respond to of 186894
 
Fred,

>re:kash,

<Your Fab is running at 10% capacity and you are losing tens of millions of dollars/quarter.>

Are you saying that the size/capacity of a Fab can not be planned in accordance with anticipated demand?? This seems backwards. Build a fab of size x and then figure out how to run it at full capacity?>

Now you've got it perfectly. That's the whole problem with the semiconductor business. New generation wafer foundries cost $1-2Bn. They are enormously profitable with the right product. And you can only run them for 4-5 years before they are out of date at best. So new capacity when it comes on-line is massive and that's why we swing from excess supply to severe shortage to excess supply. Your fixed costs are major costs, so you need to run them as close to full capacity as possible.

Most mid-size semiconductor companies go to outside wafer foundries
such as TSMC,UMC,Chartered,IBM. Very successfull outfits like Xilinx,ALtera etc use external foundry exclusively. The problem for the CPU market is that these external foundries are more expensive than your own foundry, and their fab process is optimized for general purpose applications. The CPU market is obsessed with MHZ and very agressive design rules so external foundry is not best solution either.

It takes 2-3 years from when you line the money to get the fab running. Then you must have a small development fab in the mean-time to develop that process for production 2-3 years out. Then you need a good enough design that will be competitive in 2-3 years. And you hope like hell that your competition doesn't come out with a better/faster mouse trap.

I know it's easy to take partisan slapshots at Jerry and what a crummy manager he is. But remember he's fighting a very big competitor with limited resouces and finances. The risk/rewards if they pull it off are very high, but this is a very tough business in general and the CPU wars is probably as tough as it gets.



To: Fred Fahmy who wrote (67221)10/23/1998 12:31:00 AM
From: Paul Engel  Read Replies (3) | Respond to of 186894
 
Fred & Intel Investors - Here's a good article on the XEON and the importance of very fast L2 caches.

It's a long article but worth reading. The pertinent points are that Intel has optimized the XEON for, among other things, HIGH SPEED LARGE L2 caches which make them excellent for server applications.

It also implies that the AMD K-7 with its slower speed L2 cache may not be much of a competitor to the XEON and newer versions (Cascades) when the K-7 finally does arrive.

Here's a "clip":

{======================================}

infoworld.com

"Intel's Xeon is caching in"

HOW IT WORKS. The Xeon's first incarnation runs at a
whizzing 400 MHz, and Intel recently introduced a
450-MHz version, but fast clock speeds do not tell the
whole performance story. Processors also need a
high-performance reservoir, called Level 2 (L2) cache, to
keep data fetched from main memory at the ready. If the
L2 cache is either stingy in size or doesn't pump data
quickly enough to the logical core, the processor
squanders cycles waiting for data to come down the pipe.
Intel learned this lesson when it released its basic PC
Celeron processor in April; the Celeron had no L2 cache,
and its slow speed hurt sales. Intel responded to the chilly
debut by adding L2 cache to Celeron and re-releasing it
in August to a warmer reception and brisker sales.

Cache and carry

Intel learned this lesson well. Xeon's release comes with
512KB of L2 cache; future releases will offer 1MB and
2MB options. Depending on the intended use of the
server, the importance of L2 cache size varies. For
example, if the server will run data-intensive applications
such as databases, online transaction processing, or
CAD applications, larger cache sizes are desirable. For
file-and-print servers, a smaller, 512KB cache may be
acceptable.

L2 cache also needs to be quick. Xeon's L2 cache runs
at the same clock speed as the main processor, so there
is no lag time (or latency) between the cache and the
processor. Although this feature was built into Xeon's
predecessor, the Pentium Pro, regular Pentium IIs use
half-speed L2 cache. This engineering compromise is
part of the reason that Pentium IIs don't scale well and
therefore aren't ideal as server platforms."

{==========================================}

Paul