Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Joseph Pareti who wrote (67231)	10/23/1998 3:35:00 AM
From: Tenchusatsu	Respond to of 186894

<Paul, why is L2 limited to 2 MB ? Cost reasons ? For performance reasons we see a great improvement from large caches (e.g. 8MB on 21164), although this may benefit primarily floating point-intensive apps.> I'll answer this one. I would guess Intel's own performance verification teams have decided that going from 2 to 4 MB of L2 cache makes only a little difference, not enough to justify its marginal cost. On the other hand, the Alpha 21164 has a three-level cache system. The Alpha design pretty much requires huge, multi-level caches, just like the P6 design requires a back-side L2 cache in order to perform well. Also, Alpha servers typically run in the six-figure range in terms of pricing, so Digital can afford to stick in those expensive 8 MB L3 caches. Tenchusatsu

To: Joseph Pareti who wrote (67231)	10/23/1998 9:01:00 AM
From: rudedog	Respond to of 186894

Joseph - Alpha has typically had larger cache than the 32 bit machines, partly because pulling in 64 bit data does not always bring in 64 bits of content. Comparison of performance characteristics is not straightforward between Intel's architectures and Alpha WRT either cache size or clock speed. Sure, bigger is always better, other things being equal. But getting a full-speed on-chip L2 is a huge benefit even at a smaller cache size.

To: Joseph Pareti who wrote (67231)	10/23/1998 12:08:00 PM
From: Paul Engel	Respond to of 186894

Joe - Re: " Paul, why is L2 limited to 2 MB ..." I'm not sure if there is a HARD limit at 2 MegaBytes but there are several design tradeoffs that must be made. The backside bus has to be designed to address the L2 cache. Larger caches require more address lines - increasing the overall size of the bus. With an external L2 cache (Pentium II & XEON) this also means extra bond pads and output drivers for the address lines. These all contribute to larger die sizes, increased power consumption, etc. Thus, there are physical design tradeoffs that must be made. Paul