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To: Paul Engel who wrote (67254)10/23/1998 12:52:00 PM
From: Paul Engel  Read Replies (2) | Respond to of 186894
 
CORRECTION - Re: " The Coppermine will be a 0.18 micron Katmai processor packaged in a Slot 1 configuration. This will be targeted at the Performance Desktop segment. Cascades will be limited to 2-way SMP configurations."

The last line should read: "Coppermine will be limited to 2-way SMP configurations."

Paul



To: Paul Engel who wrote (67254)10/25/1998 11:01:00 AM
From: Joseph Pareti  Read Replies (1) | Respond to of 186894
 
>The Cascades now appears to be a 0.18 micron
>Katmai processor with up to
>(Intel hasn't released the actual number)
>2 MegaBytes of ON CHIP L2 cache

2 MB on chip ? Wow ! The largest on-chip cache
I am familiar with is the 96KB S-cache on 21164 :-)

This thing should scream, do you have any details
on latency, pointers etc.
Thanks
/j


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