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To: kash johal who wrote (67378)	10/26/1998 11:43:00 AM
From: Tony Viola	Read Replies (1) \| Respond to of 186894

Kash, >>>K7 will support up to 8-way servers.<<< Two questions: 1. Where'd you see that? Tom's (Dirk's) presentation doesn't make it obvious). 2. Given that it is 8-way capable, Is that 8-way SMP, or something else? Tony

To: kash johal who wrote (67378)	10/26/1998 11:43:00 AM
From: Mary Cluney	Respond to of 186894

Kash, >>>K7 supports up to 8MB of L2 cache(could be important for servers?).<<< Is that really a smart thing to do - lose your focus in the PC market just when you may have a chance to succeed and start thinking about destablizing prices in the server market? Or is it just Jerry Sanders strategy to buy some more time with investors and creditors - so he can continue to receive huge paychecks and perks to go along with a profligate life style for a few more years. As long as investors continue to act like cheer leaders and don't mind investing money into a business without any returns for decades at a time - why not? Good Scam - if you can get it. Mary

To: kash johal who wrote (67378)	10/26/1998 1:09:00 PM
From: Tenchusatsu	Read Replies (3) \| Respond to of 186894

<K7 will support up to 8-way servers.> Wrong. K7 is plugged into a point-to-point connection, meaning that all the symmetric multiprocessing is handled by the north bridge. In other words, to have more than one K7 in a system, the north bridge must have enough P2P ports to support all those K7's. In contrast, Xeon is 4-way SMP, meaning that four processors will plug "gluelessly" into one bus, and the north bridge only has to connect to that one bus. Saying that the K7 will support up to 8-way servers is the same thing as saying that the Xeon will support up to 32-way servers. In theory, you can have an infinite amount of K7's or Xeons in one big-iron server if the system is designed to support all those processors. But I'll guarantee you that it'll be simpler to design a 4-way Xeon system than a 4-way K7 system. <K7 supports up to 8MB of L2 cache(could be important for servers?).> So? It makes no difference unless AMD is actually willing to stick 8 MB of expensive CSRAM on the Slot A daughtercard. That 8 MB figure is only because the Slot A platform is borrowed from the Digital Alpha platform. And we all know that the Alpha has up to 8 MB of L3 cache. But I don't think AMD will try for more than 2 MB of L2 cache. There are reasons why Intel isn't going for more than 2 MB of L2 cache in the Xeon platform, even though it would be trivial to design (but not trivial in terms of cost). Kash, I don't pretend to be an expert in subjects that aren't my area of expertise. Unfortunately for you, servers just happens to be mine. Tenchusatsu