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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Jim McMannis who wrote (40159)10/26/1998 6:17:00 PM
From: Maxwell  Respond to of 1573969
 
Jim:

Here is what you need for your calculation. The PII of 131mm^2 is the
333MHz-400MHz. The 450MHz is a 5% die shrink of the 131mm^2. Thus that die size is 125mm^2. Thus the 128K cache (including the redundancy) is 29mm^2 (CeleronA is built on this 5% shrunk 0.25um process). The 256K L2 would be 183mm^2 on the 5% shrunk of 0.25um process. When Intel goes to integrated 256K cache they will use 0.18um. Die size will probably reduces by 30-40%. Thus the lower bound is about 110mm^2.

Maxwell



To: Jim McMannis who wrote (40159)10/26/1998 8:51:00 PM
From: Elmer  Read Replies (1) | Respond to of 1573969
 
Re: "The 128k takes up 23mm2 of real estate but that 23mm2 has a cache controller in it I think."

Jim, the L2 cache controller has been in the die since the beginning of the P6 generation. It's not new to the Mendocino

EP


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